1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _SFC_NOR_H 8 #define _SFC_NOR_H 9 10 #include "sfc.h" 11 12 #define NOR_PAGE_SIZE 256 13 #define NOR_BLOCK_SIZE (64 * 1024) 14 #define NOR_SECS_BLK (NOR_BLOCK_SIZE / 512) 15 #define NOR_SECS_PAGE 8 16 17 #define FEA_READ_STATUE_MASK (0x3 << 0) 18 #define FEA_STATUE_MODE1 0 19 #define FEA_STATUE_MODE2 1 20 #define FEA_4BIT_READ BIT(2) 21 #define FEA_4BIT_PROG BIT(3) 22 #define FEA_4BYTE_ADDR BIT(4) 23 #define FEA_4BYTE_ADDR_MODE BIT(5) 24 25 /*Command Set*/ 26 #define CMD_READ_JEDECID (0x9F) 27 #define CMD_READ_DATA (0x03) 28 #define CMD_READ_STATUS (0x05) 29 #define CMD_WRITE_STATUS (0x01) 30 #define CMD_PAGE_PROG (0x02) 31 #define CMD_SECTOR_ERASE (0x20) 32 #define CMD_BLK64K_ERASE (0xD8) 33 #define CMD_BLK32K_ERASE (0x52) 34 #define CMD_CHIP_ERASE (0xC7) 35 #define CMD_WRITE_EN (0x06) 36 #define CMD_WRITE_DIS (0x04) 37 #define CMD_PAGE_READ (0x13) 38 #define CMD_PAGE_FASTREAD4B (0x0C) 39 #define CMD_GET_FEATURE (0x0F) 40 #define CMD_SET_FEATURE (0x1F) 41 #define CMD_PROG_LOAD (0x02) 42 #define CMD_PROG_EXEC (0x10) 43 #define CMD_BLOCK_ERASE (0xD8) 44 #define CMD_READ_DATA_X2 (0x3B) 45 #define CMD_READ_DATA_X4 (0x6B) 46 #define CMD_PROG_LOAD_X4 (0x32) 47 #define CMD_READ_STATUS2 (0x35) 48 #define CMD_READ_STATUS3 (0x15) 49 #define CMD_WRITE_STATUS2 (0x31) 50 #define CMD_WRITE_STATUS3 (0x11) 51 /* X1 cmd, X1 addr, X1 data */ 52 #define CMD_FAST_READ_X1 (0x0B) 53 /* X1 cmd, X1 addr, X2 data */ 54 #define CMD_FAST_READ_X2 (0x3B) 55 /* X1 cmd, X1 addr, X4 data SUPPORT GD MARCONIX WINBOND */ 56 #define CMD_FAST_READ_X4 (0x6B) 57 /* X1 cmd, X1 addr, X4 data SUPPORT GD MARCONIX WINBOND */ 58 #define CMD_FAST_4READ_X4 (0x6C) 59 /* X1 cmd, X4 addr, X4 data SUPPORT EON GD MARCONIX WINBOND */ 60 #define CMD_FAST_READ_A4 (0xEB) 61 /* X1 cmd, X1 addr, X4 data, SUPPORT GD WINBOND */ 62 #define CMD_PAGE_PROG_X4 (0x32) 63 /* X1 cmd, X4 addr, X4 data, SUPPORT MARCONIX */ 64 #define CMD_PAGE_PROG_A4 (0x38) 65 /* X1 cmd, X4 addr, X4 data, SUPPORT MARCONIX */ 66 #define CMD_PAGE_PROG_4PP (0x3E) 67 #define CMD_RESET_NAND (0xFF) 68 #define CMD_ENTER_4BYTE_MODE (0xB7) 69 #define CMD_EXIT_4BYTE_MODE (0xE9) 70 #define CMD_ENABLE_RESER (0x66) 71 #define CMD_RESET_DEVICE (0x99) 72 #define CMD_READ_PARAMETER (0x5A) 73 74 enum NOR_ERASE_TYPE { 75 ERASE_SECTOR = 0, 76 ERASE_BLOCK64K, 77 ERASE_CHIP 78 }; 79 80 enum SNOR_IO_MODE { 81 IO_MODE_SPI = 0, 82 IO_MODE_QPI 83 }; 84 85 enum SNOR_READ_MODE { 86 READ_MODE_NOMAL = 0, 87 READ_MODE_FAST 88 }; 89 90 enum SNOR_ADDR_MODE { 91 ADDR_MODE_3BYTE = 0, 92 ADDR_MODE_4BYTE 93 }; 94 95 typedef int (*SNOR_WRITE_STATUS)(u32 reg_index, u8 status); 96 97 struct SFNOR_DEV { 98 u32 capacity; 99 u8 manufacturer; 100 u8 mem_type; 101 u16 page_size; 102 u32 blk_size; 103 104 u8 read_cmd; 105 u8 prog_cmd; 106 u8 sec_erase_cmd; 107 u8 blk_erase_cmd; 108 u8 QE_bits; 109 110 enum SNOR_READ_MODE read_mode; 111 enum SNOR_ADDR_MODE addr_mode; 112 enum SNOR_IO_MODE io_mode; 113 114 enum SFC_DATA_LINES read_lines; 115 enum SFC_DATA_LINES prog_lines; 116 enum SFC_DATA_LINES prog_addr_lines; 117 118 SNOR_WRITE_STATUS write_status; 119 u32 max_iosize; 120 }; 121 122 struct flash_info { 123 u32 id; 124 125 u8 block_size; 126 u8 sector_size; 127 u8 read_cmd; 128 u8 prog_cmd; 129 130 u8 read_cmd_4; 131 u8 prog_cmd_4; 132 u8 sector_erase_cmd; 133 u8 block_erase_cmd; 134 135 u8 feature; 136 u8 density; /* (1 << density) sectors*/ 137 u8 QE_bits; 138 u8 reserved2; 139 }; 140 141 /* flash table packet for easy boot */ 142 #define SNOR_INFO_PACKET_ID 0x464E494E 143 #define SNOR_INFO_PACKET_HEAD_LEN 14 144 145 #define SNOR_INFO_PACKET_SPI_MODE_RATE_SHIFT 25 146 147 struct snor_info_packet { 148 u32 id; 149 u32 head_hash; /*hash for head, check by bootrom.*/ 150 u16 head_len; /*320 - 16 bytes*/ 151 u16 version; 152 u8 read_cmd; 153 u8 prog_cmd; 154 u8 read_cmd_4; 155 u8 prog_cmd_4; 156 157 u8 sector_erase_cmd; 158 u8 block_erase_cmd; 159 u8 feature; 160 u8 QE_bits; 161 162 u32 spi_mode; 163 }; 164 165 int snor_init(struct SFNOR_DEV *p_dev); 166 u32 snor_get_capacity(struct SFNOR_DEV *p_dev); 167 int snor_read(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data); 168 int snor_write(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data); 169 int snor_erase(struct SFNOR_DEV *p_dev, 170 u32 addr, 171 enum NOR_ERASE_TYPE erase_type); 172 int snor_read_id(u8 *data); 173 int snor_prog_page(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size); 174 int snor_read_data(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size); 175 int snor_reset_device(void); 176 int snor_disable_QE(struct SFNOR_DEV *p_dev); 177 int snor_reinit_from_table_packet(struct SFNOR_DEV *p_dev, 178 struct snor_info_packet *packet); 179 #endif 180