1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __SFC_NAND_H 8*4882a593Smuzhiyun #define __SFC_NAND_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include "flash_com.h" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define SFC_NAND_WAIT_TIME_OUT 3 13*4882a593Smuzhiyun #define SFC_NAND_PROG_ERASE_ERROR 2 14*4882a593Smuzhiyun #define SFC_NAND_HW_ERROR 1 15*4882a593Smuzhiyun #define SFC_NAND_ECC_ERROR NAND_ERROR 16*4882a593Smuzhiyun #define SFC_NAND_ECC_REFRESH NAND_STS_REFRESH 17*4882a593Smuzhiyun #define SFC_NAND_ECC_OK NAND_STS_OK 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define SFC_NAND_PAGE_MAX_SIZE 4224 20*4882a593Smuzhiyun #define SFC_NAND_SECTOR_FULL_SIZE 528 21*4882a593Smuzhiyun #define SFC_NAND_SECTOR_SIZE 512 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define FEA_READ_STATUE_MASK (0x3 << 0) 24*4882a593Smuzhiyun #define FEA_STATUE_MODE1 0 25*4882a593Smuzhiyun #define FEA_STATUE_MODE2 1 26*4882a593Smuzhiyun #define FEA_4BIT_READ BIT(2) 27*4882a593Smuzhiyun #define FEA_4BIT_PROG BIT(3) 28*4882a593Smuzhiyun #define FEA_4BYTE_ADDR BIT(4) 29*4882a593Smuzhiyun #define FEA_4BYTE_ADDR_MODE BIT(5) 30*4882a593Smuzhiyun #define FEA_SOFT_QOP_BIT BIT(6) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* Command Set */ 33*4882a593Smuzhiyun #define CMD_READ_JEDECID (0x9F) 34*4882a593Smuzhiyun #define CMD_READ_DATA (0x03) 35*4882a593Smuzhiyun #define CMD_READ_STATUS (0x05) 36*4882a593Smuzhiyun #define CMD_WRITE_STATUS (0x01) 37*4882a593Smuzhiyun #define CMD_PAGE_PROG (0x02) 38*4882a593Smuzhiyun #define CMD_SECTOR_ERASE (0x20) 39*4882a593Smuzhiyun #define CMD_BLK64K_ERASE (0xD8) 40*4882a593Smuzhiyun #define CMD_BLK32K_ERASE (0x52) 41*4882a593Smuzhiyun #define CMD_CHIP_ERASE (0xC7) 42*4882a593Smuzhiyun #define CMD_WRITE_EN (0x06) 43*4882a593Smuzhiyun #define CMD_WRITE_DIS (0x04) 44*4882a593Smuzhiyun #define CMD_PAGE_READ (0x13) 45*4882a593Smuzhiyun #define CMD_GET_FEATURE (0x0F) 46*4882a593Smuzhiyun #define CMD_SET_FEATURE (0x1F) 47*4882a593Smuzhiyun #define CMD_PROG_LOAD (0x02) 48*4882a593Smuzhiyun #define CMD_PROG_EXEC (0x10) 49*4882a593Smuzhiyun #define CMD_BLOCK_ERASE (0xD8) 50*4882a593Smuzhiyun #define CMD_READ_DATA_X2 (0x3B) 51*4882a593Smuzhiyun #define CMD_READ_DATA_X4 (0x6B) 52*4882a593Smuzhiyun #define CMD_PROG_LOAD_X4 (0x32) 53*4882a593Smuzhiyun #define CMD_READ_STATUS2 (0x35) 54*4882a593Smuzhiyun #define CMD_READ_STATUS3 (0x15) 55*4882a593Smuzhiyun #define CMD_WRITE_STATUS2 (0x31) 56*4882a593Smuzhiyun #define CMD_WRITE_STATUS3 (0x11) 57*4882a593Smuzhiyun #define CMD_FAST_READ_X1 (0x0B) /* X1 cmd, X1 addr, X1 data */ 58*4882a593Smuzhiyun #define CMD_FAST_READ_X2 (0x3B) /* X1 cmd, X1 addr, X2 data */ 59*4882a593Smuzhiyun /* X1 cmd, X1 addr, X4 data SUPPORT GD MARCONIX WINBOND */ 60*4882a593Smuzhiyun #define CMD_FAST_READ_X4 (0x6B) 61*4882a593Smuzhiyun /* X1 cmd, X1 addr, X4 data SUPPORT GD MARCONIX WINBOND */ 62*4882a593Smuzhiyun #define CMD_FAST_4READ_X4 (0x6C) 63*4882a593Smuzhiyun /* X1 cmd, X4 addr, X4 data SUPPORT EON GD MARCONIX WINBOND */ 64*4882a593Smuzhiyun #define CMD_FAST_READ_A4 (0xEB) 65*4882a593Smuzhiyun /* X1 cmd, X1 addr, X4 data, SUPPORT GD WINBOND */ 66*4882a593Smuzhiyun #define CMD_PAGE_PROG_X4 (0x32) 67*4882a593Smuzhiyun /* X1 cmd, X4 addr, X4 data, SUPPORT MARCONIX */ 68*4882a593Smuzhiyun #define CMD_PAGE_PROG_A4 (0x38) 69*4882a593Smuzhiyun #define CMD_RESET_NAND (0xFF) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define CMD_ENTER_4BYTE_MODE (0xB7) 72*4882a593Smuzhiyun #define CMD_EXIT_4BYTE_MODE (0xE9) 73*4882a593Smuzhiyun #define CMD_ENABLE_RESER (0x66) 74*4882a593Smuzhiyun #define CMD_RESET_DEVICE (0x99) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun struct SFNAND_DEV { 77*4882a593Smuzhiyun u32 capacity; 78*4882a593Smuzhiyun u32 block_size; 79*4882a593Smuzhiyun u16 page_size; 80*4882a593Smuzhiyun u8 manufacturer; 81*4882a593Smuzhiyun u8 mem_type; 82*4882a593Smuzhiyun u8 read_lines; 83*4882a593Smuzhiyun u8 prog_lines; 84*4882a593Smuzhiyun u8 page_read_cmd; 85*4882a593Smuzhiyun u8 page_prog_cmd; 86*4882a593Smuzhiyun u8 *recheck_buffer; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun struct nand_mega_area { 90*4882a593Smuzhiyun u8 off0; 91*4882a593Smuzhiyun u8 off1; 92*4882a593Smuzhiyun u8 off2; 93*4882a593Smuzhiyun u8 off3; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun struct nand_info { 97*4882a593Smuzhiyun u8 id0; 98*4882a593Smuzhiyun u8 id1; 99*4882a593Smuzhiyun u8 id2; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun u16 sec_per_page; 102*4882a593Smuzhiyun u16 page_per_blk; 103*4882a593Smuzhiyun u16 plane_per_die; 104*4882a593Smuzhiyun u16 blk_per_plane; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun u8 feature; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun u8 density; /* (1 << density) sectors*/ 109*4882a593Smuzhiyun u8 max_ecc_bits; 110*4882a593Smuzhiyun u8 has_qe_bits; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun struct nand_mega_area meta; 113*4882a593Smuzhiyun u32 (*ecc_status)(void); 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun extern struct nand_phy_info g_nand_phy_info; 117*4882a593Smuzhiyun extern struct nand_ops g_nand_ops; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun u32 sfc_nand_init(void); 120*4882a593Smuzhiyun void sfc_nand_deinit(void); 121*4882a593Smuzhiyun int sfc_nand_read_id(u8 *buf); 122*4882a593Smuzhiyun u32 sfc_nand_erase_block(u8 cs, u32 addr); 123*4882a593Smuzhiyun u32 sfc_nand_prog_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare); 124*4882a593Smuzhiyun u32 sfc_nand_read_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare); 125*4882a593Smuzhiyun u32 sfc_nand_prog_page_raw(u8 cs, u32 addr, u32 *p_page_buf); 126*4882a593Smuzhiyun u32 sfc_nand_read_page_raw(u8 cs, u32 addr, u32 *p_page_buf); 127*4882a593Smuzhiyun u32 sfc_nand_check_bad_block(u8 cs, u32 addr); 128*4882a593Smuzhiyun u32 sfc_nand_mark_bad_block(u8 cs, u32 addr); 129*4882a593Smuzhiyun void sfc_nand_ftl_ops_init(void); 130*4882a593Smuzhiyun struct SFNAND_DEV *sfc_nand_get_private_dev(void); 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #endif 133