1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2016, NVIDIA CORPORATION.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <dm.h>
9*4882a593Smuzhiyun #include <misc.h>
10*4882a593Smuzhiyun #include <reset-uclass.h>
11*4882a593Smuzhiyun #include <asm/arch-tegra/bpmp_abi.h>
12*4882a593Smuzhiyun
tegra186_reset_request(struct reset_ctl * reset_ctl)13*4882a593Smuzhiyun static int tegra186_reset_request(struct reset_ctl *reset_ctl)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
16*4882a593Smuzhiyun reset_ctl->dev, reset_ctl->id);
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun return 0;
19*4882a593Smuzhiyun }
20*4882a593Smuzhiyun
tegra186_reset_free(struct reset_ctl * reset_ctl)21*4882a593Smuzhiyun static int tegra186_reset_free(struct reset_ctl *reset_ctl)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
24*4882a593Smuzhiyun reset_ctl->dev, reset_ctl->id);
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun return 0;
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun
tegra186_reset_common(struct reset_ctl * reset_ctl,enum mrq_reset_commands cmd)29*4882a593Smuzhiyun static int tegra186_reset_common(struct reset_ctl *reset_ctl,
30*4882a593Smuzhiyun enum mrq_reset_commands cmd)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun struct mrq_reset_request req;
33*4882a593Smuzhiyun int ret;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun req.cmd = cmd;
36*4882a593Smuzhiyun req.reset_id = reset_ctl->id;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun ret = misc_call(reset_ctl->dev->parent, MRQ_RESET, &req, sizeof(req),
39*4882a593Smuzhiyun NULL, 0);
40*4882a593Smuzhiyun if (ret < 0)
41*4882a593Smuzhiyun return ret;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun return 0;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
tegra186_reset_assert(struct reset_ctl * reset_ctl)46*4882a593Smuzhiyun static int tegra186_reset_assert(struct reset_ctl *reset_ctl)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
49*4882a593Smuzhiyun reset_ctl->dev, reset_ctl->id);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun return tegra186_reset_common(reset_ctl, CMD_RESET_ASSERT);
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
tegra186_reset_deassert(struct reset_ctl * reset_ctl)54*4882a593Smuzhiyun static int tegra186_reset_deassert(struct reset_ctl *reset_ctl)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
57*4882a593Smuzhiyun reset_ctl->dev, reset_ctl->id);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun return tegra186_reset_common(reset_ctl, CMD_RESET_DEASSERT);
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun struct reset_ops tegra186_reset_ops = {
63*4882a593Smuzhiyun .request = tegra186_reset_request,
64*4882a593Smuzhiyun .free = tegra186_reset_free,
65*4882a593Smuzhiyun .rst_assert = tegra186_reset_assert,
66*4882a593Smuzhiyun .rst_deassert = tegra186_reset_deassert,
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun
tegra186_reset_probe(struct udevice * dev)69*4882a593Smuzhiyun static int tegra186_reset_probe(struct udevice *dev)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun debug("%s(dev=%p)\n", __func__, dev);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun return 0;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun U_BOOT_DRIVER(tegra186_reset) = {
77*4882a593Smuzhiyun .name = "tegra186_reset",
78*4882a593Smuzhiyun .id = UCLASS_RESET,
79*4882a593Smuzhiyun .probe = tegra186_reset_probe,
80*4882a593Smuzhiyun .ops = &tegra186_reset_ops,
81*4882a593Smuzhiyun };
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