1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2016, NVIDIA CORPORATION.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <dm.h>
9*4882a593Smuzhiyun #include <reset-uclass.h>
10*4882a593Smuzhiyun #include <asm/arch/clock.h>
11*4882a593Smuzhiyun #include <asm/arch-tegra/clk_rst.h>
12*4882a593Smuzhiyun
tegra_car_reset_request(struct reset_ctl * reset_ctl)13*4882a593Smuzhiyun static int tegra_car_reset_request(struct reset_ctl *reset_ctl)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
16*4882a593Smuzhiyun reset_ctl->dev, reset_ctl->id);
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /* PERIPH_ID_COUNT varies per SoC */
19*4882a593Smuzhiyun if (reset_ctl->id >= PERIPH_ID_COUNT)
20*4882a593Smuzhiyun return -EINVAL;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun return 0;
23*4882a593Smuzhiyun }
24*4882a593Smuzhiyun
tegra_car_reset_free(struct reset_ctl * reset_ctl)25*4882a593Smuzhiyun static int tegra_car_reset_free(struct reset_ctl *reset_ctl)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
28*4882a593Smuzhiyun reset_ctl->dev, reset_ctl->id);
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun return 0;
31*4882a593Smuzhiyun }
32*4882a593Smuzhiyun
tegra_car_reset_assert(struct reset_ctl * reset_ctl)33*4882a593Smuzhiyun static int tegra_car_reset_assert(struct reset_ctl *reset_ctl)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
36*4882a593Smuzhiyun reset_ctl->dev, reset_ctl->id);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun reset_set_enable(reset_ctl->id, 1);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun return 0;
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
tegra_car_reset_deassert(struct reset_ctl * reset_ctl)43*4882a593Smuzhiyun static int tegra_car_reset_deassert(struct reset_ctl *reset_ctl)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
46*4882a593Smuzhiyun reset_ctl->dev, reset_ctl->id);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun reset_set_enable(reset_ctl->id, 0);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun return 0;
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun struct reset_ops tegra_car_reset_ops = {
54*4882a593Smuzhiyun .request = tegra_car_reset_request,
55*4882a593Smuzhiyun .free = tegra_car_reset_free,
56*4882a593Smuzhiyun .rst_assert = tegra_car_reset_assert,
57*4882a593Smuzhiyun .rst_deassert = tegra_car_reset_deassert,
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun
tegra_car_reset_probe(struct udevice * dev)60*4882a593Smuzhiyun static int tegra_car_reset_probe(struct udevice *dev)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun debug("%s(dev=%p)\n", __func__, dev);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun return 0;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun U_BOOT_DRIVER(tegra_car_reset) = {
68*4882a593Smuzhiyun .name = "tegra_car_reset",
69*4882a593Smuzhiyun .id = UCLASS_RESET,
70*4882a593Smuzhiyun .probe = tegra_car_reset_probe,
71*4882a593Smuzhiyun .ops = &tegra_car_reset_ops,
72*4882a593Smuzhiyun };
73