1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Derived from linux/arch/mips/bcm63xx/reset.c:
5*4882a593Smuzhiyun * Copyright (C) 2012 Jonas Gorski <jonas.gorski@gmail.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <dm.h>
12*4882a593Smuzhiyun #include <errno.h>
13*4882a593Smuzhiyun #include <reset-uclass.h>
14*4882a593Smuzhiyun #include <asm/io.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define MAX_RESETS 32
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun struct bcm6345_reset_priv {
19*4882a593Smuzhiyun void __iomem *regs;
20*4882a593Smuzhiyun };
21*4882a593Smuzhiyun
bcm6345_reset_assert(struct reset_ctl * rst)22*4882a593Smuzhiyun static int bcm6345_reset_assert(struct reset_ctl *rst)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun struct bcm6345_reset_priv *priv = dev_get_priv(rst->dev);
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun clrbits_be32(priv->regs, BIT(rst->id));
27*4882a593Smuzhiyun mdelay(20);
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun return 0;
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun
bcm6345_reset_deassert(struct reset_ctl * rst)32*4882a593Smuzhiyun static int bcm6345_reset_deassert(struct reset_ctl *rst)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun struct bcm6345_reset_priv *priv = dev_get_priv(rst->dev);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun setbits_be32(priv->regs, BIT(rst->id));
37*4882a593Smuzhiyun mdelay(20);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun return 0;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
bcm6345_reset_free(struct reset_ctl * rst)42*4882a593Smuzhiyun static int bcm6345_reset_free(struct reset_ctl *rst)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun return 0;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
bcm6345_reset_request(struct reset_ctl * rst)47*4882a593Smuzhiyun static int bcm6345_reset_request(struct reset_ctl *rst)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun if (rst->id >= MAX_RESETS)
50*4882a593Smuzhiyun return -EINVAL;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun return bcm6345_reset_assert(rst);
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun struct reset_ops bcm6345_reset_reset_ops = {
56*4882a593Smuzhiyun .free = bcm6345_reset_free,
57*4882a593Smuzhiyun .request = bcm6345_reset_request,
58*4882a593Smuzhiyun .rst_assert = bcm6345_reset_assert,
59*4882a593Smuzhiyun .rst_deassert = bcm6345_reset_deassert,
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun static const struct udevice_id bcm6345_reset_ids[] = {
63*4882a593Smuzhiyun { .compatible = "brcm,bcm6345-reset" },
64*4882a593Smuzhiyun { /* sentinel */ }
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun
bcm6345_reset_probe(struct udevice * dev)67*4882a593Smuzhiyun static int bcm6345_reset_probe(struct udevice *dev)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun struct bcm6345_reset_priv *priv = dev_get_priv(dev);
70*4882a593Smuzhiyun fdt_addr_t addr;
71*4882a593Smuzhiyun fdt_size_t size;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun addr = devfdt_get_addr_size_index(dev, 0, &size);
74*4882a593Smuzhiyun if (addr == FDT_ADDR_T_NONE)
75*4882a593Smuzhiyun return -EINVAL;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun priv->regs = ioremap(addr, size);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun return 0;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun U_BOOT_DRIVER(bcm6345_reset) = {
83*4882a593Smuzhiyun .name = "bcm6345-reset",
84*4882a593Smuzhiyun .id = UCLASS_RESET,
85*4882a593Smuzhiyun .of_match = bcm6345_reset_ids,
86*4882a593Smuzhiyun .ops = &bcm6345_reset_reset_ops,
87*4882a593Smuzhiyun .probe = bcm6345_reset_probe,
88*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct bcm6345_reset_priv),
89*4882a593Smuzhiyun };
90