1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2017 Google, Inc
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <dm.h>
9*4882a593Smuzhiyun #include <misc.h>
10*4882a593Smuzhiyun #include <reset.h>
11*4882a593Smuzhiyun #include <reset-uclass.h>
12*4882a593Smuzhiyun #include <wdt.h>
13*4882a593Smuzhiyun #include <asm/io.h>
14*4882a593Smuzhiyun #include <asm/arch/scu_ast2500.h>
15*4882a593Smuzhiyun #include <asm/arch/wdt.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun struct ast2500_reset_priv {
20*4882a593Smuzhiyun /* WDT used to perform resets. */
21*4882a593Smuzhiyun struct udevice *wdt;
22*4882a593Smuzhiyun struct ast2500_scu *scu;
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun
ast2500_ofdata_to_platdata(struct udevice * dev)25*4882a593Smuzhiyun static int ast2500_ofdata_to_platdata(struct udevice *dev)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun struct ast2500_reset_priv *priv = dev_get_priv(dev);
28*4882a593Smuzhiyun int ret;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun ret = uclass_get_device_by_phandle(UCLASS_WDT, dev, "aspeed,wdt",
31*4882a593Smuzhiyun &priv->wdt);
32*4882a593Smuzhiyun if (ret) {
33*4882a593Smuzhiyun debug("%s: can't find WDT for reset controller", __func__);
34*4882a593Smuzhiyun return ret;
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun return 0;
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
ast2500_reset_assert(struct reset_ctl * reset_ctl)40*4882a593Smuzhiyun static int ast2500_reset_assert(struct reset_ctl *reset_ctl)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
43*4882a593Smuzhiyun u32 reset_mode, reset_mask;
44*4882a593Smuzhiyun bool reset_sdram;
45*4882a593Smuzhiyun int ret;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /*
48*4882a593Smuzhiyun * To reset SDRAM, a specifal flag in SYSRESET register
49*4882a593Smuzhiyun * needs to be enabled first
50*4882a593Smuzhiyun */
51*4882a593Smuzhiyun reset_mode = ast_reset_mode_from_flags(reset_ctl->id);
52*4882a593Smuzhiyun reset_mask = ast_reset_mask_from_flags(reset_ctl->id);
53*4882a593Smuzhiyun reset_sdram = reset_mode == WDT_CTRL_RESET_SOC &&
54*4882a593Smuzhiyun (reset_mask & WDT_RESET_SDRAM);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun if (reset_sdram) {
57*4882a593Smuzhiyun ast_scu_unlock(priv->scu);
58*4882a593Smuzhiyun setbits_le32(&priv->scu->sysreset_ctrl1,
59*4882a593Smuzhiyun SCU_SYSRESET_SDRAM_WDT);
60*4882a593Smuzhiyun ret = wdt_expire_now(priv->wdt, reset_ctl->id);
61*4882a593Smuzhiyun clrbits_le32(&priv->scu->sysreset_ctrl1,
62*4882a593Smuzhiyun SCU_SYSRESET_SDRAM_WDT);
63*4882a593Smuzhiyun ast_scu_lock(priv->scu);
64*4882a593Smuzhiyun } else {
65*4882a593Smuzhiyun ret = wdt_expire_now(priv->wdt, reset_ctl->id);
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun return ret;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
ast2500_reset_request(struct reset_ctl * reset_ctl)71*4882a593Smuzhiyun static int ast2500_reset_request(struct reset_ctl *reset_ctl)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
74*4882a593Smuzhiyun reset_ctl->dev, reset_ctl->id);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun return 0;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
ast2500_reset_probe(struct udevice * dev)79*4882a593Smuzhiyun static int ast2500_reset_probe(struct udevice *dev)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun struct ast2500_reset_priv *priv = dev_get_priv(dev);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun priv->scu = ast_get_scu();
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun return 0;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun static const struct udevice_id ast2500_reset_ids[] = {
89*4882a593Smuzhiyun { .compatible = "aspeed,ast2500-reset" },
90*4882a593Smuzhiyun { }
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun struct reset_ops ast2500_reset_ops = {
94*4882a593Smuzhiyun .rst_assert = ast2500_reset_assert,
95*4882a593Smuzhiyun .request = ast2500_reset_request,
96*4882a593Smuzhiyun };
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun U_BOOT_DRIVER(ast2500_reset) = {
99*4882a593Smuzhiyun .name = "ast2500_reset",
100*4882a593Smuzhiyun .id = UCLASS_RESET,
101*4882a593Smuzhiyun .of_match = ast2500_reset_ids,
102*4882a593Smuzhiyun .probe = ast2500_reset_probe,
103*4882a593Smuzhiyun .ops = &ast2500_reset_ops,
104*4882a593Smuzhiyun .ofdata_to_platdata = ast2500_ofdata_to_platdata,
105*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct ast2500_reset_priv),
106*4882a593Smuzhiyun };
107