1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <dm.h>
9*4882a593Smuzhiyun #include <ram.h>
10*4882a593Smuzhiyun #include <syscon.h>
11*4882a593Smuzhiyun #include <asm/arch/clock.h>
12*4882a593Smuzhiyun #include <asm/arch/grf_rk3128.h>
13*4882a593Smuzhiyun #include <asm/arch/sdram.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
16*4882a593Smuzhiyun struct dram_info {
17*4882a593Smuzhiyun struct ram_info info;
18*4882a593Smuzhiyun struct rk3128_grf *grf;
19*4882a593Smuzhiyun };
20*4882a593Smuzhiyun
rk3128_dmc_probe(struct udevice * dev)21*4882a593Smuzhiyun static int rk3128_dmc_probe(struct udevice *dev)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun struct dram_info *priv = dev_get_priv(dev);
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
26*4882a593Smuzhiyun debug("%s: grf=%p\n", __func__, priv->grf);
27*4882a593Smuzhiyun priv->info.base = CONFIG_SYS_SDRAM_BASE;
28*4882a593Smuzhiyun priv->info.size = rockchip_sdram_size(
29*4882a593Smuzhiyun (phys_addr_t)&priv->grf->os_reg[1]);
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun return 0;
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun
rk3128_dmc_get_info(struct udevice * dev,struct ram_info * info)34*4882a593Smuzhiyun static int rk3128_dmc_get_info(struct udevice *dev, struct ram_info *info)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun struct dram_info *priv = dev_get_priv(dev);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun *info = priv->info;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun return 0;
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun static struct ram_ops rk3128_dmc_ops = {
44*4882a593Smuzhiyun .get_info = rk3128_dmc_get_info,
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun static const struct udevice_id rk3128_dmc_ids[] = {
49*4882a593Smuzhiyun { .compatible = "rockchip,rk3128-dmc" },
50*4882a593Smuzhiyun { }
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun U_BOOT_DRIVER(dmc_rk3128) = {
54*4882a593Smuzhiyun .name = "rockchip_rk3128_dmc",
55*4882a593Smuzhiyun .id = UCLASS_RAM,
56*4882a593Smuzhiyun .of_match = rk3128_dmc_ids,
57*4882a593Smuzhiyun .ops = &rk3128_dmc_ops,
58*4882a593Smuzhiyun .probe = rk3128_dmc_probe,
59*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct dram_info),
60*4882a593Smuzhiyun };
61