1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * (C) Copyright 2018 Rockchip Electronics Co., Ltd.
4 */
5
6 #include <common.h>
7 #include <ram.h>
8 #include <asm/io.h>
9 #include <asm/arch/sdram.h>
10 #include <asm/arch/sdram_pctl_px30.h>
11
12 /*
13 * rank = 1: cs0
14 * rank = 2: cs1
15 */
pctl_read_mr(void __iomem * pctl_base,u32 rank,u32 mr_num)16 void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num)
17 {
18 writel((rank << 4) | (1 << 0), pctl_base + DDR_PCTL2_MRCTRL0);
19 writel((mr_num << 8), pctl_base + DDR_PCTL2_MRCTRL1);
20 setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31);
21 while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31))
22 continue;
23 while (readl(pctl_base + DDR_PCTL2_MRSTAT) & PCTL2_MR_WR_BUSY)
24 continue;
25 }
26
27 /* rank = 1: cs0
28 * rank = 2: cs1
29 * rank = 3: cs0 & cs1
30 * note: be careful of keep mr original val
31 */
pctl_write_mr(void __iomem * pctl_base,u32 rank,u32 mr_num,u32 arg,u32 dramtype)32 int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg,
33 u32 dramtype)
34 {
35 while (readl(pctl_base + DDR_PCTL2_MRSTAT) & PCTL2_MR_WR_BUSY)
36 continue;
37 if (dramtype == DDR3 || dramtype == DDR4) {
38 writel((mr_num << 12) | (rank << 4) | (0 << 0),
39 pctl_base + DDR_PCTL2_MRCTRL0);
40 writel(arg, pctl_base + DDR_PCTL2_MRCTRL1);
41 } else {
42 writel((rank << 4) | (0 << 0),
43 pctl_base + DDR_PCTL2_MRCTRL0);
44 writel((mr_num << 8) | (arg & 0xff),
45 pctl_base + DDR_PCTL2_MRCTRL1);
46 }
47
48 setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31);
49 while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31))
50 continue;
51 while (readl(pctl_base + DDR_PCTL2_MRSTAT) & PCTL2_MR_WR_BUSY)
52 continue;
53
54 return 0;
55 }
56
57 /*
58 * rank : 1:cs0, 2:cs1, 3:cs0&cs1
59 * vrefrate: 4500: 45%,
60 */
pctl_write_vrefdq(void __iomem * pctl_base,u32 rank,u32 vrefrate,u32 dramtype)61 int pctl_write_vrefdq(void __iomem *pctl_base, u32 rank, u32 vrefrate,
62 u32 dramtype)
63 {
64 u32 tccd_l, value;
65 u32 dis_auto_zq = 0;
66
67 if (dramtype != DDR4 || vrefrate < 4500 || vrefrate > 9250)
68 return (-1);
69
70 tccd_l = (readl(pctl_base + DDR_PCTL2_DRAMTMG4) >> 16) & 0xf;
71 tccd_l = (tccd_l - 4) << 10;
72
73 if (vrefrate > 7500) {
74 /* range 1 */
75 value = ((vrefrate - 6000) / 65) | tccd_l;
76 } else {
77 /* range 2 */
78 value = ((vrefrate - 4500) / 65) | tccd_l | (1 << 6);
79 }
80
81 dis_auto_zq = pctl_dis_zqcs_aref(pctl_base);
82
83 /* enable vrefdq calibratin */
84 pctl_write_mr(pctl_base, rank, 6, value | (1 << 7), dramtype);
85 udelay(1);/* tvrefdqe */
86 /* write vrefdq value */
87 pctl_write_mr(pctl_base, rank, 6, value | (1 << 7), dramtype);
88 udelay(1);/* tvref_time */
89 pctl_write_mr(pctl_base, rank, 6, value | (0 << 7), dramtype);
90 udelay(1);/* tvrefdqx */
91
92 pctl_rest_zqcs_aref(pctl_base, dis_auto_zq);
93
94 return 0;
95 }
96
upctl2_update_ref_reg(void __iomem * pctl_base)97 static int upctl2_update_ref_reg(void __iomem *pctl_base)
98 {
99 u32 ret;
100
101 ret = readl(pctl_base + DDR_PCTL2_RFSHCTL3) ^ (1 << 1);
102 writel(ret, pctl_base + DDR_PCTL2_RFSHCTL3);
103
104 return 0;
105 }
106
pctl_dis_zqcs_aref(void __iomem * pctl_base)107 u32 pctl_dis_zqcs_aref(void __iomem *pctl_base)
108 {
109 u32 dis_auto_zq = 0;
110
111 /* disable zqcs */
112 if (!(readl(pctl_base + DDR_PCTL2_ZQCTL0) &
113 (1ul << 31))) {
114 dis_auto_zq = 1;
115 setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
116 }
117
118 /* disable auto refresh */
119 setbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
120
121 upctl2_update_ref_reg(pctl_base);
122
123 return dis_auto_zq;
124 }
125
pctl_rest_zqcs_aref(void __iomem * pctl_base,u32 dis_auto_zq)126 void pctl_rest_zqcs_aref(void __iomem *pctl_base, u32 dis_auto_zq)
127 {
128 /* restore zqcs */
129 if (dis_auto_zq)
130 clrbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
131
132 /* restore auto refresh */
133 clrbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
134
135 upctl2_update_ref_reg(pctl_base);
136 }
137
pctl_remodify_sdram_params(struct ddr_pctl_regs * pctl_regs,struct sdram_cap_info * cap_info,u32 dram_type)138 u32 pctl_remodify_sdram_params(struct ddr_pctl_regs *pctl_regs,
139 struct sdram_cap_info *cap_info,
140 u32 dram_type)
141 {
142 u32 tmp = 0, tmp_adr = 0, i;
143
144 for (i = 0; pctl_regs->pctl[i][0] != 0xFFFFFFFF; i++) {
145 if (pctl_regs->pctl[i][0] == 0) {
146 tmp = pctl_regs->pctl[i][1];/* MSTR */
147 tmp_adr = i;
148 }
149 }
150
151 tmp &= ~((3ul << 30) | (3ul << 24) | (3ul << 12));
152
153 switch (cap_info->dbw) {
154 case 2:
155 tmp |= (3ul << 30);
156 break;
157 case 1:
158 tmp |= (2ul << 30);
159 break;
160 case 0:
161 default:
162 tmp |= (1ul << 30);
163 break;
164 }
165
166 /* active_ranks always keep 2 rank for dfi monitor */
167 tmp |= 3 << 24;
168
169 tmp |= (2 - cap_info->bw) << 12;
170
171 pctl_regs->pctl[tmp_adr][1] = tmp;
172
173 return 0;
174 }
175
pctl_cfg(void __iomem * pctl_base,struct ddr_pctl_regs * pctl_regs,u32 sr_idle,u32 pd_idle)176 int pctl_cfg(void __iomem *pctl_base, struct ddr_pctl_regs *pctl_regs,
177 u32 sr_idle, u32 pd_idle)
178 {
179 u32 i;
180
181 for (i = 0; pctl_regs->pctl[i][0] != 0xFFFFFFFF; i++) {
182 writel(pctl_regs->pctl[i][1],
183 pctl_base + pctl_regs->pctl[i][0]);
184 }
185 clrsetbits_le32(pctl_base + DDR_PCTL2_PWRTMG,
186 (0xff << 16) | 0x1f,
187 ((sr_idle & 0xff) << 16) | (pd_idle & 0x1f));
188
189 clrsetbits_le32(pctl_base + DDR_PCTL2_HWLPCTL,
190 0xfff << 16,
191 5 << 16);
192 /* disable zqcs */
193 setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1u << 31);
194
195 return 0;
196 }
197
198