1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * (C) Copyright 2018 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <common.h>
7*4882a593Smuzhiyun #include <dm.h>
8*4882a593Smuzhiyun #include <ram.h>
9*4882a593Smuzhiyun #include <syscon.h>
10*4882a593Smuzhiyun #include <asm/arch/clock.h>
11*4882a593Smuzhiyun #include <asm/arch/grf_px30.h>
12*4882a593Smuzhiyun #include <asm/arch/grf_rv1108.h>
13*4882a593Smuzhiyun #include <asm/arch/grf_rk1808.h>
14*4882a593Smuzhiyun #include <asm/arch/grf_rk3036.h>
15*4882a593Smuzhiyun #include <asm/arch/grf_rk3308.h>
16*4882a593Smuzhiyun #include <asm/arch/rockchip_dmc.h>
17*4882a593Smuzhiyun #include <asm/arch/sdram.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #ifndef CONFIG_TPL_BUILD
22*4882a593Smuzhiyun struct dram_info {
23*4882a593Smuzhiyun struct ram_info info;
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun
dmc_probe(struct udevice * dev)26*4882a593Smuzhiyun static int dmc_probe(struct udevice *dev)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun int ret = 0;
29*4882a593Smuzhiyun struct dram_info *priv = dev_get_priv(dev);
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun if (!(gd->flags & GD_FLG_RELOC)) {
32*4882a593Smuzhiyun #if defined(CONFIG_ROCKCHIP_RV1108)
33*4882a593Smuzhiyun struct rv1108_grf *grf =
34*4882a593Smuzhiyun syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun priv->info.size =
37*4882a593Smuzhiyun rockchip_sdram_size((phys_addr_t)&grf->os_reg2);
38*4882a593Smuzhiyun #elif defined(CONFIG_ROCKCHIP_RK3036)
39*4882a593Smuzhiyun struct rk3036_grf *grf =
40*4882a593Smuzhiyun syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun priv->info.size =
43*4882a593Smuzhiyun rockchip_sdram_size((phys_addr_t)&grf->os_reg[1]);
44*4882a593Smuzhiyun #elif defined(CONFIG_ROCKCHIP_RK3308)
45*4882a593Smuzhiyun struct rk3308_grf *grf =
46*4882a593Smuzhiyun syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun priv->info.size =
49*4882a593Smuzhiyun rockchip_sdram_size((phys_addr_t)&grf->os_reg2);
50*4882a593Smuzhiyun #elif defined(CONFIG_ROCKCHIP_PX30)
51*4882a593Smuzhiyun struct px30_pmugrf *pmugrf =
52*4882a593Smuzhiyun syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun priv->info.size =
55*4882a593Smuzhiyun rockchip_sdram_size((phys_addr_t)&pmugrf->os_reg[2]);
56*4882a593Smuzhiyun #elif defined(CONFIG_ROCKCHIP_RK1808)
57*4882a593Smuzhiyun struct rk1808_pmugrf *pmugrf =
58*4882a593Smuzhiyun syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun priv->info.size =
61*4882a593Smuzhiyun rockchip_sdram_size((phys_addr_t)&pmugrf->os_reg[2]);
62*4882a593Smuzhiyun #else
63*4882a593Smuzhiyun #error chip error
64*4882a593Smuzhiyun #endif
65*4882a593Smuzhiyun priv->info.base = CONFIG_SYS_SDRAM_BASE;
66*4882a593Smuzhiyun } else {
67*4882a593Smuzhiyun #if defined(CONFIG_ROCKCHIP_PX30)
68*4882a593Smuzhiyun #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ROCKCHIP_DMC)
69*4882a593Smuzhiyun ret = rockchip_dmcfreq_probe(dev);
70*4882a593Smuzhiyun #endif
71*4882a593Smuzhiyun #endif
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun return ret;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
dmc_get_info(struct udevice * dev,struct ram_info * info)77*4882a593Smuzhiyun static int dmc_get_info(struct udevice *dev, struct ram_info *info)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun struct dram_info *priv = dev_get_priv(dev);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun *info = priv->info;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun return 0;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun static struct ram_ops dmc_ops = {
87*4882a593Smuzhiyun .get_info = dmc_get_info,
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun static const struct udevice_id dmc_ids[] = {
91*4882a593Smuzhiyun #if defined(CONFIG_ROCKCHIP_RV1108)
92*4882a593Smuzhiyun { .compatible = "rockchip,rv1108-dmc" },
93*4882a593Smuzhiyun #elif defined(CONFIG_ROCKCHIP_RK3036)
94*4882a593Smuzhiyun { .compatible = "rockchip,rk3036-dmc" },
95*4882a593Smuzhiyun #elif defined(CONFIG_ROCKCHIP_RK3308)
96*4882a593Smuzhiyun { .compatible = "rockchip,rk3308-dmc" },
97*4882a593Smuzhiyun #elif defined(CONFIG_ROCKCHIP_PX30)
98*4882a593Smuzhiyun { .compatible = "rockchip,px30-dmc" },
99*4882a593Smuzhiyun #elif defined(CONFIG_ROCKCHIP_RK1808)
100*4882a593Smuzhiyun { .compatible = "rockchip,rk1808-dmc" },
101*4882a593Smuzhiyun #endif
102*4882a593Smuzhiyun { }
103*4882a593Smuzhiyun };
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun U_BOOT_DRIVER(dmc_tiny) = {
106*4882a593Smuzhiyun .name = "rockchip_dmc",
107*4882a593Smuzhiyun .id = UCLASS_RAM,
108*4882a593Smuzhiyun .of_match = dmc_ids,
109*4882a593Smuzhiyun .ops = &dmc_ops,
110*4882a593Smuzhiyun .probe = dmc_probe,
111*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct dram_info),
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun #endif
114