1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2006 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Dave Liu <daveliu@freescale.com> 5*4882a593Smuzhiyun * based on source code of Shlomi Gridish 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __UCCF_H__ 11*4882a593Smuzhiyun #define __UCCF_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include "common.h" 14*4882a593Smuzhiyun #include "linux/immap_qe.h" 15*4882a593Smuzhiyun #include <fsl_qe.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* Fast or Giga ethernet 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun typedef enum enet_type { 20*4882a593Smuzhiyun FAST_ETH, 21*4882a593Smuzhiyun GIGA_ETH, 22*4882a593Smuzhiyun } enet_type_e; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* General UCC Extended Mode Register 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun #define UCC_GUEMR_MODE_MASK_RX 0x02 27*4882a593Smuzhiyun #define UCC_GUEMR_MODE_MASK_TX 0x01 28*4882a593Smuzhiyun #define UCC_GUEMR_MODE_FAST_RX 0x02 29*4882a593Smuzhiyun #define UCC_GUEMR_MODE_FAST_TX 0x01 30*4882a593Smuzhiyun #define UCC_GUEMR_MODE_SLOW_RX 0x00 31*4882a593Smuzhiyun #define UCC_GUEMR_MODE_SLOW_TX 0x00 32*4882a593Smuzhiyun #define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 must be set 1 */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* General UCC FAST Mode Register 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun #define UCC_FAST_GUMR_TCI 0x20000000 37*4882a593Smuzhiyun #define UCC_FAST_GUMR_TRX 0x10000000 38*4882a593Smuzhiyun #define UCC_FAST_GUMR_TTX 0x08000000 39*4882a593Smuzhiyun #define UCC_FAST_GUMR_CDP 0x04000000 40*4882a593Smuzhiyun #define UCC_FAST_GUMR_CTSP 0x02000000 41*4882a593Smuzhiyun #define UCC_FAST_GUMR_CDS 0x01000000 42*4882a593Smuzhiyun #define UCC_FAST_GUMR_CTSS 0x00800000 43*4882a593Smuzhiyun #define UCC_FAST_GUMR_TXSY 0x00020000 44*4882a593Smuzhiyun #define UCC_FAST_GUMR_RSYN 0x00010000 45*4882a593Smuzhiyun #define UCC_FAST_GUMR_RTSM 0x00002000 46*4882a593Smuzhiyun #define UCC_FAST_GUMR_REVD 0x00000400 47*4882a593Smuzhiyun #define UCC_FAST_GUMR_ENR 0x00000020 48*4882a593Smuzhiyun #define UCC_FAST_GUMR_ENT 0x00000010 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* GUMR [MODE] bit maps 51*4882a593Smuzhiyun */ 52*4882a593Smuzhiyun #define UCC_FAST_GUMR_HDLC 0x00000000 53*4882a593Smuzhiyun #define UCC_FAST_GUMR_QMC 0x00000002 54*4882a593Smuzhiyun #define UCC_FAST_GUMR_UART 0x00000004 55*4882a593Smuzhiyun #define UCC_FAST_GUMR_BISYNC 0x00000008 56*4882a593Smuzhiyun #define UCC_FAST_GUMR_ATM 0x0000000a 57*4882a593Smuzhiyun #define UCC_FAST_GUMR_ETH 0x0000000c 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* Transmit On Demand (UTORD) 60*4882a593Smuzhiyun */ 61*4882a593Smuzhiyun #define UCC_SLOW_TOD 0x8000 62*4882a593Smuzhiyun #define UCC_FAST_TOD 0x8000 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* Fast Ethernet (10/100 Mbps) 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun #define UCC_GETH_URFS_INIT 512 /* Rx virtual FIFO size */ 67*4882a593Smuzhiyun #define UCC_GETH_URFET_INIT 256 /* 1/2 urfs */ 68*4882a593Smuzhiyun #define UCC_GETH_URFSET_INIT 384 /* 3/4 urfs */ 69*4882a593Smuzhiyun #define UCC_GETH_UTFS_INIT 512 /* Tx virtual FIFO size */ 70*4882a593Smuzhiyun #define UCC_GETH_UTFET_INIT 256 /* 1/2 utfs */ 71*4882a593Smuzhiyun #define UCC_GETH_UTFTT_INIT 128 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* Gigabit Ethernet (1000 Mbps) 74*4882a593Smuzhiyun */ 75*4882a593Smuzhiyun #define UCC_GETH_URFS_GIGA_INIT 4096/*2048*/ /* Rx virtual FIFO size */ 76*4882a593Smuzhiyun #define UCC_GETH_URFET_GIGA_INIT 2048/*1024*/ /* 1/2 urfs */ 77*4882a593Smuzhiyun #define UCC_GETH_URFSET_GIGA_INIT 3072/*1536*/ /* 3/4 urfs */ 78*4882a593Smuzhiyun #define UCC_GETH_UTFS_GIGA_INIT 8192/*2048*/ /* Tx virtual FIFO size */ 79*4882a593Smuzhiyun #define UCC_GETH_UTFET_GIGA_INIT 4096/*1024*/ /* 1/2 utfs */ 80*4882a593Smuzhiyun #define UCC_GETH_UTFTT_GIGA_INIT 0x400/*0x40*/ /* */ 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* UCC fast alignment 83*4882a593Smuzhiyun */ 84*4882a593Smuzhiyun #define UCC_FAST_RX_ALIGN 4 85*4882a593Smuzhiyun #define UCC_FAST_MRBLR_ALIGNMENT 4 86*4882a593Smuzhiyun #define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT 8 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* Sizes 89*4882a593Smuzhiyun */ 90*4882a593Smuzhiyun #define UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD 8 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* UCC fast structure. 93*4882a593Smuzhiyun */ 94*4882a593Smuzhiyun typedef struct ucc_fast_info { 95*4882a593Smuzhiyun int ucc_num; 96*4882a593Smuzhiyun qe_clock_e rx_clock; 97*4882a593Smuzhiyun qe_clock_e tx_clock; 98*4882a593Smuzhiyun enet_type_e eth_type; 99*4882a593Smuzhiyun } ucc_fast_info_t; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun typedef struct ucc_fast_private { 102*4882a593Smuzhiyun ucc_fast_info_t *uf_info; 103*4882a593Smuzhiyun ucc_fast_t *uf_regs; /* a pointer to memory map of UCC regs */ 104*4882a593Smuzhiyun u32 *p_ucce; /* a pointer to the event register */ 105*4882a593Smuzhiyun u32 *p_uccm; /* a pointer to the mask register */ 106*4882a593Smuzhiyun int enabled_tx; /* whether UCC is enabled for Tx (ENT) */ 107*4882a593Smuzhiyun int enabled_rx; /* whether UCC is enabled for Rx (ENR) */ 108*4882a593Smuzhiyun u32 ucc_fast_tx_virtual_fifo_base_offset; 109*4882a593Smuzhiyun u32 ucc_fast_rx_virtual_fifo_base_offset; 110*4882a593Smuzhiyun } ucc_fast_private_t; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf); 113*4882a593Smuzhiyun u32 ucc_fast_get_qe_cr_subblock(int ucc_num); 114*4882a593Smuzhiyun void ucc_fast_enable(ucc_fast_private_t *uccf, comm_dir_e mode); 115*4882a593Smuzhiyun void ucc_fast_disable(ucc_fast_private_t *uccf, comm_dir_e mode); 116*4882a593Smuzhiyun int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t **uccf_ret); 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #endif /* __UCCF_H__ */ 119