1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2016 Google Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <dm.h>
9*4882a593Smuzhiyun #include <pwm.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include <asm/arch/clock.h>
12*4882a593Smuzhiyun #include <asm/arch/pwm.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun struct tegra_pwm_priv {
17*4882a593Smuzhiyun struct pwm_ctlr *regs;
18*4882a593Smuzhiyun };
19*4882a593Smuzhiyun
tegra_pwm_set_config(struct udevice * dev,uint channel,uint period_ns,uint duty_ns)20*4882a593Smuzhiyun static int tegra_pwm_set_config(struct udevice *dev, uint channel,
21*4882a593Smuzhiyun uint period_ns, uint duty_ns)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun struct tegra_pwm_priv *priv = dev_get_priv(dev);
24*4882a593Smuzhiyun struct pwm_ctlr *regs = priv->regs;
25*4882a593Smuzhiyun uint pulse_width;
26*4882a593Smuzhiyun u32 reg;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun if (channel >= 4)
29*4882a593Smuzhiyun return -EINVAL;
30*4882a593Smuzhiyun debug("%s: Configure '%s' channel %u\n", __func__, dev->name, channel);
31*4882a593Smuzhiyun /* We ignore the period here and just use 32KHz */
32*4882a593Smuzhiyun clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, 32768);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun pulse_width = duty_ns * 255 / period_ns;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun reg = pulse_width << PWM_WIDTH_SHIFT;
37*4882a593Smuzhiyun reg |= 1 << PWM_DIVIDER_SHIFT;
38*4882a593Smuzhiyun writel(reg, ®s[channel].control);
39*4882a593Smuzhiyun debug("%s: pulse_width=%u\n", __func__, pulse_width);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun return 0;
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
tegra_pwm_set_enable(struct udevice * dev,uint channel,bool enable)44*4882a593Smuzhiyun static int tegra_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun struct tegra_pwm_priv *priv = dev_get_priv(dev);
47*4882a593Smuzhiyun struct pwm_ctlr *regs = priv->regs;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun if (channel >= 4)
50*4882a593Smuzhiyun return -EINVAL;
51*4882a593Smuzhiyun debug("%s: Enable '%s' channel %u\n", __func__, dev->name, channel);
52*4882a593Smuzhiyun clrsetbits_le32(®s[channel].control, PWM_ENABLE_MASK,
53*4882a593Smuzhiyun enable ? PWM_ENABLE_MASK : 0);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun return 0;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
tegra_pwm_ofdata_to_platdata(struct udevice * dev)58*4882a593Smuzhiyun static int tegra_pwm_ofdata_to_platdata(struct udevice *dev)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun struct tegra_pwm_priv *priv = dev_get_priv(dev);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun priv->regs = (struct pwm_ctlr *)dev_read_addr(dev);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun return 0;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun static const struct pwm_ops tegra_pwm_ops = {
68*4882a593Smuzhiyun .set_config = tegra_pwm_set_config,
69*4882a593Smuzhiyun .set_enable = tegra_pwm_set_enable,
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun static const struct udevice_id tegra_pwm_ids[] = {
73*4882a593Smuzhiyun { .compatible = "nvidia,tegra124-pwm" },
74*4882a593Smuzhiyun { .compatible = "nvidia,tegra20-pwm" },
75*4882a593Smuzhiyun { }
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun U_BOOT_DRIVER(tegra_pwm) = {
79*4882a593Smuzhiyun .name = "tegra_pwm",
80*4882a593Smuzhiyun .id = UCLASS_PWM,
81*4882a593Smuzhiyun .of_match = tegra_pwm_ids,
82*4882a593Smuzhiyun .ops = &tegra_pwm_ops,
83*4882a593Smuzhiyun .ofdata_to_platdata = tegra_pwm_ofdata_to_platdata,
84*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct tegra_pwm_priv),
85*4882a593Smuzhiyun };
86