1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2014
3*4882a593Smuzhiyun * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Basic support for the pwm module on imx6.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <div64.h>
12*4882a593Smuzhiyun #include <pwm.h>
13*4882a593Smuzhiyun #include <asm/arch/imx-regs.h>
14*4882a593Smuzhiyun #include <asm/io.h>
15*4882a593Smuzhiyun #include "pwm-imx-util.h"
16*4882a593Smuzhiyun
pwm_init(int pwm_id,int div,int invert)17*4882a593Smuzhiyun int pwm_init(int pwm_id, int div, int invert)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun if (!pwm)
22*4882a593Smuzhiyun return -1;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun writel(0, &pwm->ir);
25*4882a593Smuzhiyun return 0;
26*4882a593Smuzhiyun }
27*4882a593Smuzhiyun
pwm_config(int pwm_id,int duty_ns,int period_ns)28*4882a593Smuzhiyun int pwm_config(int pwm_id, int duty_ns, int period_ns)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
31*4882a593Smuzhiyun unsigned long period_cycles, duty_cycles, prescale;
32*4882a593Smuzhiyun u32 cr;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun if (!pwm)
35*4882a593Smuzhiyun return -1;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun pwm_imx_get_parms(period_ns, duty_ns, &period_cycles, &duty_cycles,
38*4882a593Smuzhiyun &prescale);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun cr = PWMCR_PRESCALER(prescale) |
41*4882a593Smuzhiyun PWMCR_DOZEEN | PWMCR_WAITEN |
42*4882a593Smuzhiyun PWMCR_DBGEN | PWMCR_CLKSRC_IPG_HIGH;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun writel(cr, &pwm->cr);
45*4882a593Smuzhiyun /* set duty cycles */
46*4882a593Smuzhiyun writel(duty_cycles, &pwm->sar);
47*4882a593Smuzhiyun /* set period cycles */
48*4882a593Smuzhiyun writel(period_cycles, &pwm->pr);
49*4882a593Smuzhiyun return 0;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
pwm_enable(int pwm_id)52*4882a593Smuzhiyun int pwm_enable(int pwm_id)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun if (!pwm)
57*4882a593Smuzhiyun return -1;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun setbits_le32(&pwm->cr, PWMCR_EN);
60*4882a593Smuzhiyun return 0;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
pwm_disable(int pwm_id)63*4882a593Smuzhiyun void pwm_disable(int pwm_id)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun if (!pwm)
68*4882a593Smuzhiyun return;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun clrbits_le32(&pwm->cr, PWMCR_EN);
71*4882a593Smuzhiyun }
72