1*4882a593Smuzhiyunconfig DM_PWM 2*4882a593Smuzhiyun bool "Enable support for pulse-width modulation devices (PWM)" 3*4882a593Smuzhiyun depends on DM 4*4882a593Smuzhiyun help 5*4882a593Smuzhiyun A pulse-width modulator emits a pulse of varying width and provides 6*4882a593Smuzhiyun control over the duty cycle (high and low time) of the signal. This 7*4882a593Smuzhiyun is often used to control a voltage level. The more time the PWM 8*4882a593Smuzhiyun spends in the 'high' state, the higher the voltage. The PWM's 9*4882a593Smuzhiyun frequency/period can be controlled along with the proportion of that 10*4882a593Smuzhiyun time that the signal is high. 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunconfig PWM_EXYNOS 13*4882a593Smuzhiyun bool "Enable support for the Exynos PWM" 14*4882a593Smuzhiyun depends on DM_PWM 15*4882a593Smuzhiyun help 16*4882a593Smuzhiyun This PWM is found on Samsung Exynos 5250 and other Samsung SoCs. It 17*4882a593Smuzhiyun supports a programmable period and duty cycle. A 32-bit counter is 18*4882a593Smuzhiyun used. It provides 5 channels which can be independently 19*4882a593Smuzhiyun programmed. Channel 4 (the last) is normally used as a timer. 20*4882a593Smuzhiyun 21*4882a593Smuzhiyunconfig PWM_ROCKCHIP 22*4882a593Smuzhiyun bool "Enable support for the Rockchip PWM" 23*4882a593Smuzhiyun depends on DM_PWM 24*4882a593Smuzhiyun help 25*4882a593Smuzhiyun This PWM is found on RK3288 and other Rockchip SoCs. It supports a 26*4882a593Smuzhiyun programmable period and duty cycle. A 32-bit counter is used. 27*4882a593Smuzhiyun Various options provided in the hardware (such as capture mode and 28*4882a593Smuzhiyun continuous/single-shot) are not supported by the driver. 29*4882a593Smuzhiyun 30*4882a593Smuzhiyunconfig PWM_SANDBOX 31*4882a593Smuzhiyun bool "Enable support for the sandbox PWM" 32*4882a593Smuzhiyun help 33*4882a593Smuzhiyun This is a sandbox PWM used for testing. It provides 3 channels and 34*4882a593Smuzhiyun records the settings passed into it, but otherwise does nothing 35*4882a593Smuzhiyun useful. The PWM can be enabled but is not connected to any outputs 36*4882a593Smuzhiyun so this is not very useful. 37*4882a593Smuzhiyun 38*4882a593Smuzhiyunconfig PWM_TEGRA 39*4882a593Smuzhiyun bool "Enable support for the Tegra PWM" 40*4882a593Smuzhiyun depends on DM_PWM 41*4882a593Smuzhiyun help 42*4882a593Smuzhiyun This PWM is found on Tegra 20 and other Nvidia SoCs. It supports 43*4882a593Smuzhiyun four channels with a programmable period and duty cycle. Only a 44*4882a593Smuzhiyun 32KHz clock is supported by the driver but the duty cycle is 45*4882a593Smuzhiyun configurable. 46