xref: /OK3568_Linux_fs/u-boot/drivers/power/regulator/palmas_regulator.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * (C) Copyright 2016
3*4882a593Smuzhiyun  * Texas Instruments Incorporated, <www.ti.com>
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Keerthy <j-keerthy@ti.com>
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <fdtdec.h>
12*4882a593Smuzhiyun #include <errno.h>
13*4882a593Smuzhiyun #include <dm.h>
14*4882a593Smuzhiyun #include <i2c.h>
15*4882a593Smuzhiyun #include <power/pmic.h>
16*4882a593Smuzhiyun #include <power/regulator.h>
17*4882a593Smuzhiyun #include <power/palmas.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #define	REGULATOR_ON		0x1
22*4882a593Smuzhiyun #define	REGULATOR_OFF		0x0
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #define	SMPS_MODE_MASK		0x3
25*4882a593Smuzhiyun #define	SMPS_MODE_SHIFT		0x0
26*4882a593Smuzhiyun #define	LDO_MODE_MASK		0x1
27*4882a593Smuzhiyun #define	LDO_MODE_SHIFT		0x0
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun static const char palmas_smps_ctrl[][PALMAS_SMPS_NUM] = {
30*4882a593Smuzhiyun 	{0x20, 0x24, 0x28, 0x2c, 0x30, 0x34, 0x38, 0x3c},
31*4882a593Smuzhiyun 	{0x20, 0x24, 0x28, 0x2c, 0x30, 0x34, 0x38},
32*4882a593Smuzhiyun 	{0x20, 0x24, 0x2c, 0x30, 0x38},
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun static const char palmas_smps_volt[][PALMAS_SMPS_NUM] = {
36*4882a593Smuzhiyun 	{0x23, 0x27, 0x2b, 0x2f, 0x33, 0x37, 0x3b, 0x3c},
37*4882a593Smuzhiyun 	{0x23, 0x27, 0x2b, 0x2f, 0x33, 0x37, 0x3b},
38*4882a593Smuzhiyun 	{0x23, 0x27, 0x2f, 0x33, 0x3B}
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun static const char palmas_ldo_ctrl[][PALMAS_LDO_NUM] = {
42*4882a593Smuzhiyun 	{0x50, 0x52, 0x54, 0x56, 0x58, 0x5a, 0x5c, 0x5e, 0x60, 0x62, 0x64},
43*4882a593Smuzhiyun 	{0x50, 0x52, 0x54, 0x56, 0x58, 0x5a, 0x5c, 0x5e, 0x60, 0x62, 0x64},
44*4882a593Smuzhiyun 	{0x50, 0x52, 0x54, 0x5e, 0x62}
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun static const char palmas_ldo_volt[][PALMAS_LDO_NUM] = {
48*4882a593Smuzhiyun 	{0x51, 0x53, 0x55, 0x57, 0x59, 0x5b, 0x5d, 0x5f, 0x61, 0x63, 0x65},
49*4882a593Smuzhiyun 	{0x51, 0x53, 0x55, 0x57, 0x59, 0x5b, 0x5d, 0x5f, 0x61, 0x63, 0x65},
50*4882a593Smuzhiyun 	{0x51, 0x53, 0x55, 0x5f, 0x63}
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun 
palmas_smps_enable(struct udevice * dev,int op,bool * enable)53*4882a593Smuzhiyun static int palmas_smps_enable(struct udevice *dev, int op, bool *enable)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun 	int ret;
56*4882a593Smuzhiyun 	unsigned int adr;
57*4882a593Smuzhiyun 	struct dm_regulator_uclass_platdata *uc_pdata;
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 	uc_pdata = dev_get_uclass_platdata(dev);
60*4882a593Smuzhiyun 	adr = uc_pdata->ctrl_reg;
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	ret = pmic_reg_read(dev->parent, adr);
63*4882a593Smuzhiyun 		if (ret < 0)
64*4882a593Smuzhiyun 			return ret;
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 	if (op == PMIC_OP_GET) {
67*4882a593Smuzhiyun 		ret &= PALMAS_SMPS_STATUS_MASK;
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 		if (ret)
70*4882a593Smuzhiyun 			*enable = true;
71*4882a593Smuzhiyun 		else
72*4882a593Smuzhiyun 			*enable = false;
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 		return 0;
75*4882a593Smuzhiyun 	} else if (op == PMIC_OP_SET) {
76*4882a593Smuzhiyun 		if (*enable)
77*4882a593Smuzhiyun 			ret |= PALMAS_SMPS_MODE_MASK;
78*4882a593Smuzhiyun 		else
79*4882a593Smuzhiyun 			ret &= ~(PALMAS_SMPS_MODE_MASK);
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 		ret = pmic_reg_write(dev->parent, adr, ret);
82*4882a593Smuzhiyun 		if (ret)
83*4882a593Smuzhiyun 			return ret;
84*4882a593Smuzhiyun 	}
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	return 0;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun 
palmas_smps_volt2hex(int uV)89*4882a593Smuzhiyun static int palmas_smps_volt2hex(int uV)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun 	if (uV > PALMAS_LDO_VOLT_MAX)
92*4882a593Smuzhiyun 		return -EINVAL;
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	if (uV > 1650000)
95*4882a593Smuzhiyun 		return (uV - 1000000) / 20000 + 0x6;
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	if (uV == 500000)
98*4882a593Smuzhiyun 		return 0x6;
99*4882a593Smuzhiyun 	else
100*4882a593Smuzhiyun 		return 0x6 + ((uV - 500000) / 10000);
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun 
palmas_smps_hex2volt(int hex,bool range)103*4882a593Smuzhiyun static int palmas_smps_hex2volt(int hex, bool range)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun 	unsigned int uV = 0;
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	if (hex > PALMAS_SMPS_VOLT_MAX_HEX)
108*4882a593Smuzhiyun 		return -EINVAL;
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	if (hex < 0x7)
111*4882a593Smuzhiyun 		uV = 500000;
112*4882a593Smuzhiyun 	else
113*4882a593Smuzhiyun 		uV = 500000 + (hex - 0x6) * 10000;
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	if (range)
116*4882a593Smuzhiyun 		uV *= 2;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	return uV;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun 
palmas_smps_val(struct udevice * dev,int op,int * uV)121*4882a593Smuzhiyun static int palmas_smps_val(struct udevice *dev, int op, int *uV)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun 	unsigned int hex, adr;
124*4882a593Smuzhiyun 	int ret;
125*4882a593Smuzhiyun 	bool range;
126*4882a593Smuzhiyun 	struct dm_regulator_uclass_platdata *uc_pdata;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	uc_pdata = dev_get_uclass_platdata(dev);
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	if (op == PMIC_OP_GET)
131*4882a593Smuzhiyun 		*uV = 0;
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	adr = uc_pdata->volt_reg;
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	ret = pmic_reg_read(dev->parent, adr);
136*4882a593Smuzhiyun 	if (ret < 0)
137*4882a593Smuzhiyun 		return ret;
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	if (op == PMIC_OP_GET) {
140*4882a593Smuzhiyun 		if (ret & PALMAS_SMPS_RANGE_MASK)
141*4882a593Smuzhiyun 			range =  true;
142*4882a593Smuzhiyun 		else
143*4882a593Smuzhiyun 			range = false;
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 		ret &= PALMAS_SMPS_VOLT_MASK;
146*4882a593Smuzhiyun 		ret = palmas_smps_hex2volt(ret, range);
147*4882a593Smuzhiyun 		if (ret < 0)
148*4882a593Smuzhiyun 			return ret;
149*4882a593Smuzhiyun 		*uV = ret;
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 		return 0;
152*4882a593Smuzhiyun 	}
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	hex = palmas_smps_volt2hex(*uV);
155*4882a593Smuzhiyun 	if (hex < 0)
156*4882a593Smuzhiyun 		return hex;
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	ret &= ~PALMAS_SMPS_VOLT_MASK;
159*4882a593Smuzhiyun 	ret |= hex;
160*4882a593Smuzhiyun 	if (*uV > 1650000)
161*4882a593Smuzhiyun 		ret |= PALMAS_SMPS_RANGE_MASK;
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	return pmic_reg_write(dev->parent, adr, ret);
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun 
palmas_ldo_bypass_enable(struct udevice * dev,bool enabled)166*4882a593Smuzhiyun static int palmas_ldo_bypass_enable(struct udevice *dev, bool enabled)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun 	int type = dev_get_driver_data(dev_get_parent(dev));
169*4882a593Smuzhiyun 	struct dm_regulator_uclass_platdata *p;
170*4882a593Smuzhiyun 	unsigned int adr;
171*4882a593Smuzhiyun 	int reg;
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	if (type == TPS65917) {
174*4882a593Smuzhiyun 		/* bypass available only on LDO1 and LDO2 */
175*4882a593Smuzhiyun 		if (dev->driver_data > 2)
176*4882a593Smuzhiyun 			return -ENOTSUPP;
177*4882a593Smuzhiyun 	} else if (type == TPS659038) {
178*4882a593Smuzhiyun 		/* bypass available only on LDO9 */
179*4882a593Smuzhiyun 		if (dev->driver_data != 9)
180*4882a593Smuzhiyun 			return -ENOTSUPP;
181*4882a593Smuzhiyun 	}
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	p = dev_get_uclass_platdata(dev);
184*4882a593Smuzhiyun 	adr = p->ctrl_reg;
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	reg = pmic_reg_read(dev->parent, adr);
187*4882a593Smuzhiyun 	if (reg < 0)
188*4882a593Smuzhiyun 		return reg;
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 	if (enabled)
191*4882a593Smuzhiyun 		reg |= PALMAS_LDO_BYPASS_EN;
192*4882a593Smuzhiyun 	else
193*4882a593Smuzhiyun 		reg &= ~PALMAS_LDO_BYPASS_EN;
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	return pmic_reg_write(dev->parent, adr, reg);
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun 
palmas_ldo_enable(struct udevice * dev,int op,bool * enable)198*4882a593Smuzhiyun static int palmas_ldo_enable(struct udevice *dev, int op, bool *enable)
199*4882a593Smuzhiyun {
200*4882a593Smuzhiyun 	int ret;
201*4882a593Smuzhiyun 	unsigned int adr;
202*4882a593Smuzhiyun 	struct dm_regulator_uclass_platdata *uc_pdata;
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	uc_pdata = dev_get_uclass_platdata(dev);
205*4882a593Smuzhiyun 	adr = uc_pdata->ctrl_reg;
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	ret = pmic_reg_read(dev->parent, adr);
208*4882a593Smuzhiyun 		if (ret < 0)
209*4882a593Smuzhiyun 			return ret;
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	if (op == PMIC_OP_GET) {
212*4882a593Smuzhiyun 		ret &= PALMAS_LDO_STATUS_MASK;
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 		if (ret)
215*4882a593Smuzhiyun 			*enable = true;
216*4882a593Smuzhiyun 		else
217*4882a593Smuzhiyun 			*enable = false;
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 		return 0;
220*4882a593Smuzhiyun 	} else if (op == PMIC_OP_SET) {
221*4882a593Smuzhiyun 		if (*enable)
222*4882a593Smuzhiyun 			ret |= PALMAS_LDO_MODE_MASK;
223*4882a593Smuzhiyun 		else
224*4882a593Smuzhiyun 			ret &= ~(PALMAS_LDO_MODE_MASK);
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 		ret = pmic_reg_write(dev->parent, adr, ret);
227*4882a593Smuzhiyun 		if (ret)
228*4882a593Smuzhiyun 			return ret;
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun 		ret = palmas_ldo_bypass_enable(dev, false);
231*4882a593Smuzhiyun 		if (ret && (ret != -ENOTSUPP))
232*4882a593Smuzhiyun 			return ret;
233*4882a593Smuzhiyun 	}
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun 	return 0;
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun 
palmas_ldo_volt2hex(int uV)238*4882a593Smuzhiyun static int palmas_ldo_volt2hex(int uV)
239*4882a593Smuzhiyun {
240*4882a593Smuzhiyun 	if (uV > PALMAS_LDO_VOLT_MAX)
241*4882a593Smuzhiyun 		return -EINVAL;
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	return (uV - 850000) / 50000;
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun 
palmas_ldo_hex2volt(int hex)246*4882a593Smuzhiyun static int palmas_ldo_hex2volt(int hex)
247*4882a593Smuzhiyun {
248*4882a593Smuzhiyun 	if (hex > PALMAS_LDO_VOLT_MAX_HEX)
249*4882a593Smuzhiyun 		return -EINVAL;
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 	if (!hex)
252*4882a593Smuzhiyun 		return 0;
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	return (hex * 50000) + 850000;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun 
palmas_ldo_val(struct udevice * dev,int op,int * uV)257*4882a593Smuzhiyun static int palmas_ldo_val(struct udevice *dev, int op, int *uV)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun 	unsigned int hex, adr;
260*4882a593Smuzhiyun 	int ret;
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	struct dm_regulator_uclass_platdata *uc_pdata;
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 	if (op == PMIC_OP_GET)
265*4882a593Smuzhiyun 		*uV = 0;
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun 	uc_pdata = dev_get_uclass_platdata(dev);
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	adr = uc_pdata->volt_reg;
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	ret = pmic_reg_read(dev->parent, adr);
272*4882a593Smuzhiyun 	if (ret < 0)
273*4882a593Smuzhiyun 		return ret;
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun 	if (op == PMIC_OP_GET) {
276*4882a593Smuzhiyun 		ret &= PALMAS_LDO_VOLT_MASK;
277*4882a593Smuzhiyun 		ret = palmas_ldo_hex2volt(ret);
278*4882a593Smuzhiyun 		if (ret < 0)
279*4882a593Smuzhiyun 			return ret;
280*4882a593Smuzhiyun 		*uV = ret;
281*4882a593Smuzhiyun 		return 0;
282*4882a593Smuzhiyun 	}
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun 	hex = palmas_ldo_volt2hex(*uV);
285*4882a593Smuzhiyun 	if (hex < 0)
286*4882a593Smuzhiyun 		return hex;
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun 	ret &= ~PALMAS_LDO_VOLT_MASK;
289*4882a593Smuzhiyun 	ret |= hex;
290*4882a593Smuzhiyun 	if (*uV > 1650000)
291*4882a593Smuzhiyun 		ret |= 0x80;
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 	return pmic_reg_write(dev->parent, adr, ret);
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun 
palmas_ldo_probe(struct udevice * dev)296*4882a593Smuzhiyun static int palmas_ldo_probe(struct udevice *dev)
297*4882a593Smuzhiyun {
298*4882a593Smuzhiyun 	struct dm_regulator_uclass_platdata *uc_pdata;
299*4882a593Smuzhiyun 	struct udevice *parent;
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun 	uc_pdata = dev_get_uclass_platdata(dev);
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun 	parent = dev_get_parent(dev);
304*4882a593Smuzhiyun 	int type = dev_get_driver_data(parent);
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun 	uc_pdata->type = REGULATOR_TYPE_LDO;
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun 	if (dev->driver_data) {
309*4882a593Smuzhiyun 		u8 idx = dev->driver_data - 1;
310*4882a593Smuzhiyun 		uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][idx];
311*4882a593Smuzhiyun 		uc_pdata->volt_reg = palmas_ldo_volt[type][idx];
312*4882a593Smuzhiyun 	} else {
313*4882a593Smuzhiyun 		/* check for ldoln and ldousb cases */
314*4882a593Smuzhiyun 		if (!strcmp("ldoln", dev->name)) {
315*4882a593Smuzhiyun 			uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][9];
316*4882a593Smuzhiyun 			uc_pdata->volt_reg = palmas_ldo_volt[type][9];
317*4882a593Smuzhiyun 		} else if (!strcmp("ldousb", dev->name)) {
318*4882a593Smuzhiyun 			uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][10];
319*4882a593Smuzhiyun 			uc_pdata->volt_reg = palmas_ldo_volt[type][10];
320*4882a593Smuzhiyun 		}
321*4882a593Smuzhiyun 	}
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun 	return 0;
324*4882a593Smuzhiyun }
325*4882a593Smuzhiyun 
ldo_get_value(struct udevice * dev)326*4882a593Smuzhiyun static int ldo_get_value(struct udevice *dev)
327*4882a593Smuzhiyun {
328*4882a593Smuzhiyun 	int uV;
329*4882a593Smuzhiyun 	int ret;
330*4882a593Smuzhiyun 
331*4882a593Smuzhiyun 	ret = palmas_ldo_val(dev, PMIC_OP_GET, &uV);
332*4882a593Smuzhiyun 	if (ret)
333*4882a593Smuzhiyun 		return ret;
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun 	return uV;
336*4882a593Smuzhiyun }
337*4882a593Smuzhiyun 
ldo_set_value(struct udevice * dev,int uV)338*4882a593Smuzhiyun static int ldo_set_value(struct udevice *dev, int uV)
339*4882a593Smuzhiyun {
340*4882a593Smuzhiyun 	return palmas_ldo_val(dev, PMIC_OP_SET, &uV);
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun 
ldo_get_enable(struct udevice * dev)343*4882a593Smuzhiyun static int ldo_get_enable(struct udevice *dev)
344*4882a593Smuzhiyun {
345*4882a593Smuzhiyun 	bool enable = false;
346*4882a593Smuzhiyun 	int ret;
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun 	ret = palmas_ldo_enable(dev, PMIC_OP_GET, &enable);
349*4882a593Smuzhiyun 	if (ret)
350*4882a593Smuzhiyun 		return ret;
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun 	return enable;
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun 
ldo_set_enable(struct udevice * dev,bool enable)355*4882a593Smuzhiyun static int ldo_set_enable(struct udevice *dev, bool enable)
356*4882a593Smuzhiyun {
357*4882a593Smuzhiyun 	return palmas_ldo_enable(dev, PMIC_OP_SET, &enable);
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun 
palmas_smps_probe(struct udevice * dev)360*4882a593Smuzhiyun static int palmas_smps_probe(struct udevice *dev)
361*4882a593Smuzhiyun {
362*4882a593Smuzhiyun 	struct dm_regulator_uclass_platdata *uc_pdata;
363*4882a593Smuzhiyun 	struct udevice *parent;
364*4882a593Smuzhiyun 	int idx;
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun 	uc_pdata = dev_get_uclass_platdata(dev);
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun 	parent = dev_get_parent(dev);
369*4882a593Smuzhiyun 	int type = dev_get_driver_data(parent);
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun 	uc_pdata->type = REGULATOR_TYPE_BUCK;
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun 	switch (type) {
374*4882a593Smuzhiyun 	case PALMAS:
375*4882a593Smuzhiyun 	case TPS659038:
376*4882a593Smuzhiyun 		switch (dev->driver_data) {
377*4882a593Smuzhiyun 		case 123:
378*4882a593Smuzhiyun 		case 12:
379*4882a593Smuzhiyun 			uc_pdata->ctrl_reg = palmas_smps_ctrl[type][0];
380*4882a593Smuzhiyun 			uc_pdata->volt_reg = palmas_smps_volt[type][0];
381*4882a593Smuzhiyun 			break;
382*4882a593Smuzhiyun 		case 3:
383*4882a593Smuzhiyun 			uc_pdata->ctrl_reg = palmas_smps_ctrl[type][1];
384*4882a593Smuzhiyun 			uc_pdata->volt_reg = palmas_smps_volt[type][1];
385*4882a593Smuzhiyun 			break;
386*4882a593Smuzhiyun 		case 45:
387*4882a593Smuzhiyun 			uc_pdata->ctrl_reg = palmas_smps_ctrl[type][2];
388*4882a593Smuzhiyun 			uc_pdata->volt_reg = palmas_smps_volt[type][2];
389*4882a593Smuzhiyun 			break;
390*4882a593Smuzhiyun 		case 6:
391*4882a593Smuzhiyun 		case 7:
392*4882a593Smuzhiyun 		case 8:
393*4882a593Smuzhiyun 		case 9:
394*4882a593Smuzhiyun 		case 10:
395*4882a593Smuzhiyun 			idx = dev->driver_data - 3;
396*4882a593Smuzhiyun 			uc_pdata->ctrl_reg = palmas_smps_ctrl[type][idx];
397*4882a593Smuzhiyun 			uc_pdata->volt_reg = palmas_smps_volt[type][idx];
398*4882a593Smuzhiyun 			break;
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 		default:
401*4882a593Smuzhiyun 			printf("Wrong ID for regulator\n");
402*4882a593Smuzhiyun 		}
403*4882a593Smuzhiyun 		break;
404*4882a593Smuzhiyun 
405*4882a593Smuzhiyun 	case TPS65917:
406*4882a593Smuzhiyun 		switch (dev->driver_data) {
407*4882a593Smuzhiyun 		case 1:
408*4882a593Smuzhiyun 		case 2:
409*4882a593Smuzhiyun 		case 3:
410*4882a593Smuzhiyun 		case 4:
411*4882a593Smuzhiyun 		case 5:
412*4882a593Smuzhiyun 			idx = dev->driver_data - 1;
413*4882a593Smuzhiyun 			uc_pdata->ctrl_reg = palmas_smps_ctrl[type][idx];
414*4882a593Smuzhiyun 			uc_pdata->volt_reg = palmas_smps_volt[type][idx];
415*4882a593Smuzhiyun 			break;
416*4882a593Smuzhiyun 		case 12:
417*4882a593Smuzhiyun 			idx = 0;
418*4882a593Smuzhiyun 			uc_pdata->ctrl_reg = palmas_smps_ctrl[type][idx];
419*4882a593Smuzhiyun 			uc_pdata->volt_reg = palmas_smps_volt[type][idx];
420*4882a593Smuzhiyun 			break;
421*4882a593Smuzhiyun 		default:
422*4882a593Smuzhiyun 			printf("Wrong ID for regulator\n");
423*4882a593Smuzhiyun 		}
424*4882a593Smuzhiyun 		break;
425*4882a593Smuzhiyun 
426*4882a593Smuzhiyun 	default:
427*4882a593Smuzhiyun 			printf("Invalid PMIC ID\n");
428*4882a593Smuzhiyun 	}
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun 	return 0;
431*4882a593Smuzhiyun }
432*4882a593Smuzhiyun 
smps_get_value(struct udevice * dev)433*4882a593Smuzhiyun static int smps_get_value(struct udevice *dev)
434*4882a593Smuzhiyun {
435*4882a593Smuzhiyun 	int uV;
436*4882a593Smuzhiyun 	int ret;
437*4882a593Smuzhiyun 
438*4882a593Smuzhiyun 	ret = palmas_smps_val(dev, PMIC_OP_GET, &uV);
439*4882a593Smuzhiyun 	if (ret)
440*4882a593Smuzhiyun 		return ret;
441*4882a593Smuzhiyun 
442*4882a593Smuzhiyun 	return uV;
443*4882a593Smuzhiyun }
444*4882a593Smuzhiyun 
smps_set_value(struct udevice * dev,int uV)445*4882a593Smuzhiyun static int smps_set_value(struct udevice *dev, int uV)
446*4882a593Smuzhiyun {
447*4882a593Smuzhiyun 	return palmas_smps_val(dev, PMIC_OP_SET, &uV);
448*4882a593Smuzhiyun }
449*4882a593Smuzhiyun 
smps_get_enable(struct udevice * dev)450*4882a593Smuzhiyun static int smps_get_enable(struct udevice *dev)
451*4882a593Smuzhiyun {
452*4882a593Smuzhiyun 	bool enable = false;
453*4882a593Smuzhiyun 	int ret;
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun 	ret = palmas_smps_enable(dev, PMIC_OP_GET, &enable);
456*4882a593Smuzhiyun 	if (ret)
457*4882a593Smuzhiyun 		return ret;
458*4882a593Smuzhiyun 
459*4882a593Smuzhiyun 	return enable;
460*4882a593Smuzhiyun }
461*4882a593Smuzhiyun 
smps_set_enable(struct udevice * dev,bool enable)462*4882a593Smuzhiyun static int smps_set_enable(struct udevice *dev, bool enable)
463*4882a593Smuzhiyun {
464*4882a593Smuzhiyun 	return palmas_smps_enable(dev, PMIC_OP_SET, &enable);
465*4882a593Smuzhiyun }
466*4882a593Smuzhiyun 
467*4882a593Smuzhiyun static const struct dm_regulator_ops palmas_ldo_ops = {
468*4882a593Smuzhiyun 	.get_value  = ldo_get_value,
469*4882a593Smuzhiyun 	.set_value  = ldo_set_value,
470*4882a593Smuzhiyun 	.get_enable = ldo_get_enable,
471*4882a593Smuzhiyun 	.set_enable = ldo_set_enable,
472*4882a593Smuzhiyun };
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun U_BOOT_DRIVER(palmas_ldo) = {
475*4882a593Smuzhiyun 	.name = PALMAS_LDO_DRIVER,
476*4882a593Smuzhiyun 	.id = UCLASS_REGULATOR,
477*4882a593Smuzhiyun 	.ops = &palmas_ldo_ops,
478*4882a593Smuzhiyun 	.probe = palmas_ldo_probe,
479*4882a593Smuzhiyun };
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun static const struct dm_regulator_ops palmas_smps_ops = {
482*4882a593Smuzhiyun 	.get_value  = smps_get_value,
483*4882a593Smuzhiyun 	.set_value  = smps_set_value,
484*4882a593Smuzhiyun 	.get_enable = smps_get_enable,
485*4882a593Smuzhiyun 	.set_enable = smps_set_enable,
486*4882a593Smuzhiyun };
487*4882a593Smuzhiyun 
488*4882a593Smuzhiyun U_BOOT_DRIVER(palmas_smps) = {
489*4882a593Smuzhiyun 	.name = PALMAS_SMPS_DRIVER,
490*4882a593Smuzhiyun 	.id = UCLASS_REGULATOR,
491*4882a593Smuzhiyun 	.ops = &palmas_smps_ops,
492*4882a593Smuzhiyun 	.probe = palmas_smps_probe,
493*4882a593Smuzhiyun };
494