1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun #include <common.h>
6*4882a593Smuzhiyun #include <dm.h>
7*4882a593Smuzhiyun #include <errno.h>
8*4882a593Smuzhiyun #include <asm/gpio.h>
9*4882a593Smuzhiyun #include <power/regulator.h>
10*4882a593Smuzhiyun #include <i2c.h>
11*4882a593Smuzhiyun #include <asm/arch/clock.h>
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun #include <syscon.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /* Voltage setting */
18*4882a593Smuzhiyun #define FAN53555_VSEL0 0x00
19*4882a593Smuzhiyun #define FAN53555_VSEL1 0x01
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define TCS452X_VSEL0 0x11
22*4882a593Smuzhiyun #define TCS452X_VSEL1 0x10
23*4882a593Smuzhiyun #define TCS452X_TIME 0x13
24*4882a593Smuzhiyun #define TCS452X_COMMAND 0x14
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* Control register */
27*4882a593Smuzhiyun #define FAN53555_CONTROL 0x02
28*4882a593Smuzhiyun /* IC Type */
29*4882a593Smuzhiyun #define FAN53555_ID1 0x03
30*4882a593Smuzhiyun /* IC mask version */
31*4882a593Smuzhiyun #define FAN53555_ID2 0x04
32*4882a593Smuzhiyun /* Monitor register */
33*4882a593Smuzhiyun #define FAN53555_MONITOR 0x05
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* VSEL bit definitions */
36*4882a593Smuzhiyun #define VSEL_BUCK_EN BIT(7)
37*4882a593Smuzhiyun #define VSEL_MODE BIT(6)
38*4882a593Smuzhiyun #define VSEL_NSEL_MASK 0x3F
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* Chip ID and Version */
41*4882a593Smuzhiyun #define DIE_ID 0x0F/* ID1 */
42*4882a593Smuzhiyun #define DIE_REV 0x0F/* ID2 */
43*4882a593Smuzhiyun /* Control bit definitions */
44*4882a593Smuzhiyun #define CTL_OUTPUT_DISCHG BIT(7)
45*4882a593Smuzhiyun #define CTL_SLEW_MASK (0x7 << 4)
46*4882a593Smuzhiyun #define CTL_SLEW_SHIFT 4
47*4882a593Smuzhiyun #define CTL_RESET BIT(2)
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #define TCS_VSEL_NSEL_MASK 0x7f
50*4882a593Smuzhiyun #define TCS_VSEL0_MODE BIT(7)
51*4882a593Smuzhiyun #define TCS_VSEL1_MODE BIT(6)
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun #define TCS_SLEW_SHIFT 3
54*4882a593Smuzhiyun #define TCS_SLEW_MASK (0x3 < 3)
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun #define FAN53555_NVOLTAGES_64 64/* Numbers of voltages */
57*4882a593Smuzhiyun #define FAN53555_NVOLTAGES_127 127/* Numbers of voltages */
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun enum fan53555_vendor {
60*4882a593Smuzhiyun FAN53555_VENDOR_FAIRCHILD = 0,
61*4882a593Smuzhiyun FAN53555_VENDOR_SILERGY,
62*4882a593Smuzhiyun FAN53555_VENDOR_TCS,
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* IC Type */
66*4882a593Smuzhiyun enum {
67*4882a593Smuzhiyun FAN53555_CHIP_ID_00 = 0,
68*4882a593Smuzhiyun FAN53555_CHIP_ID_01,
69*4882a593Smuzhiyun FAN53555_CHIP_ID_02,
70*4882a593Smuzhiyun FAN53555_CHIP_ID_03,
71*4882a593Smuzhiyun FAN53555_CHIP_ID_04,
72*4882a593Smuzhiyun FAN53555_CHIP_ID_05,
73*4882a593Smuzhiyun FAN53555_CHIP_ID_08 = 8,
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /* IC mask revision */
77*4882a593Smuzhiyun enum {
78*4882a593Smuzhiyun FAN53555_CHIP_REV_00 = 0x3,
79*4882a593Smuzhiyun FAN53555_CHIP_REV_13 = 0xf,
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun enum {
83*4882a593Smuzhiyun SILERGY_SYR82X = 8,
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun enum {
87*4882a593Smuzhiyun FAN53555_VSEL_ID_0 = 0,
88*4882a593Smuzhiyun FAN53555_VSEL_ID_1,
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun struct fan53555_regulator_info {
92*4882a593Smuzhiyun enum fan53555_vendor vendor;
93*4882a593Smuzhiyun struct udevice *dev;
94*4882a593Smuzhiyun /* IC Type and Rev */
95*4882a593Smuzhiyun int chip_id;
96*4882a593Smuzhiyun int chip_rev;
97*4882a593Smuzhiyun /* Voltage setting register */
98*4882a593Smuzhiyun unsigned int vol_reg;
99*4882a593Smuzhiyun unsigned int sleep_reg;
100*4882a593Smuzhiyun unsigned int mode_reg;
101*4882a593Smuzhiyun unsigned int vol_mask;
102*4882a593Smuzhiyun unsigned int mode_mask;
103*4882a593Smuzhiyun /* Voltage range and step(linear) */
104*4882a593Smuzhiyun unsigned int vsel_min;
105*4882a593Smuzhiyun unsigned int vsel_step;
106*4882a593Smuzhiyun struct gpio_desc vsel_gpio;
107*4882a593Smuzhiyun unsigned int sleep_vsel_id;
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun
fan53555_write(struct udevice * dev,uint reg,const uint8_t * buff,int len)110*4882a593Smuzhiyun static int fan53555_write(struct udevice *dev, uint reg, const uint8_t *buff,
111*4882a593Smuzhiyun int len)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun int ret;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun ret = dm_i2c_write(dev, reg, buff, len);
116*4882a593Smuzhiyun if (ret) {
117*4882a593Smuzhiyun debug("%s: write reg 0x%02x failed, ret=%d\n",
118*4882a593Smuzhiyun __func__, reg, ret);
119*4882a593Smuzhiyun return ret;
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun return 0;
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun
fan53555_read(struct udevice * dev,uint reg,uint8_t * buff,int len)125*4882a593Smuzhiyun static int fan53555_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun int ret;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun ret = dm_i2c_read(dev, reg, buff, len);
130*4882a593Smuzhiyun if (ret) {
131*4882a593Smuzhiyun debug("%s: read reg 0x%02x failed, ret=%d\n",
132*4882a593Smuzhiyun __func__, reg, ret);
133*4882a593Smuzhiyun return ret;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun return 0;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun
fan53555_reg_read(struct udevice * dev,uint reg)139*4882a593Smuzhiyun int fan53555_reg_read(struct udevice *dev, uint reg)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun u8 byte;
142*4882a593Smuzhiyun int ret;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun debug("%s: reg=%x", __func__, reg);
145*4882a593Smuzhiyun ret = fan53555_read(dev, reg, &byte, 1);
146*4882a593Smuzhiyun debug(", value=%x, ret=%d\n", byte, ret);
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun return ret ? ret : byte;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
fan53555_reg_write(struct udevice * dev,uint reg,uint value)151*4882a593Smuzhiyun int fan53555_reg_write(struct udevice *dev, uint reg, uint value)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun u8 byte = value;
154*4882a593Smuzhiyun int ret;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun debug("%s: reg=%x, value=%x", __func__, reg, value);
157*4882a593Smuzhiyun ret = fan53555_write(dev, reg, &byte, 1);
158*4882a593Smuzhiyun debug(", ret=%d\n", ret);
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun return ret;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun
fan53555_clrsetbits(struct udevice * dev,uint reg,uint clr,uint set)163*4882a593Smuzhiyun int fan53555_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun u8 byte;
166*4882a593Smuzhiyun int ret;
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun ret = fan53555_reg_read(dev, reg);
169*4882a593Smuzhiyun if (ret < 0)
170*4882a593Smuzhiyun return ret;
171*4882a593Smuzhiyun byte = (ret & ~clr) | set;
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun return fan53555_reg_write(dev, reg, byte);
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun
fan53555_regulator_set_enable(struct udevice * dev,bool enable)176*4882a593Smuzhiyun static int fan53555_regulator_set_enable(struct udevice *dev, bool enable)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun struct fan53555_regulator_info *priv = dev_get_priv(dev);
179*4882a593Smuzhiyun int val, sleep_vsel_id;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun if (enable) {
182*4882a593Smuzhiyun val = VSEL_BUCK_EN;
183*4882a593Smuzhiyun sleep_vsel_id = !priv->sleep_vsel_id;
184*4882a593Smuzhiyun } else {
185*4882a593Smuzhiyun val = 0;
186*4882a593Smuzhiyun sleep_vsel_id = priv->sleep_vsel_id;
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun if (dm_gpio_is_valid(&priv->vsel_gpio)) {
190*4882a593Smuzhiyun dm_gpio_set_value(&priv->vsel_gpio, sleep_vsel_id);
191*4882a593Smuzhiyun return 0;
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun fan53555_clrsetbits(dev, priv->vol_reg, VSEL_BUCK_EN, val);
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun return 0;
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun
fan53555_regulator_get_enable(struct udevice * dev)198*4882a593Smuzhiyun static int fan53555_regulator_get_enable(struct udevice *dev)
199*4882a593Smuzhiyun {
200*4882a593Smuzhiyun struct fan53555_regulator_info *priv = dev_get_priv(dev);
201*4882a593Smuzhiyun int val;
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun if (dm_gpio_is_valid(&priv->vsel_gpio)) {
204*4882a593Smuzhiyun if (priv->sleep_vsel_id)
205*4882a593Smuzhiyun return !dm_gpio_get_value(&priv->vsel_gpio);
206*4882a593Smuzhiyun else
207*4882a593Smuzhiyun return dm_gpio_get_value(&priv->vsel_gpio);
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun val = fan53555_reg_read(dev, priv->vol_reg);
211*4882a593Smuzhiyun if (val & VSEL_BUCK_EN)
212*4882a593Smuzhiyun return 1;
213*4882a593Smuzhiyun else
214*4882a593Smuzhiyun return 0;
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun
fan53555_regulator_set_suspend_enable(struct udevice * dev,bool enable)217*4882a593Smuzhiyun static int fan53555_regulator_set_suspend_enable(struct udevice *dev,
218*4882a593Smuzhiyun bool enable)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun struct fan53555_regulator_info *priv = dev_get_priv(dev);
221*4882a593Smuzhiyun int val;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun if (enable)
224*4882a593Smuzhiyun val = VSEL_BUCK_EN;
225*4882a593Smuzhiyun else
226*4882a593Smuzhiyun val = 0;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun fan53555_clrsetbits(dev, priv->sleep_reg, VSEL_BUCK_EN, val);
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun return 0;
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun
fan53555_regulator_get_suspend_enable(struct udevice * dev)233*4882a593Smuzhiyun static int fan53555_regulator_get_suspend_enable(struct udevice *dev)
234*4882a593Smuzhiyun {
235*4882a593Smuzhiyun struct fan53555_regulator_info *priv = dev_get_priv(dev);
236*4882a593Smuzhiyun int val;
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun val = fan53555_reg_read(dev, priv->sleep_reg);
239*4882a593Smuzhiyun if (val & VSEL_BUCK_EN)
240*4882a593Smuzhiyun return 1;
241*4882a593Smuzhiyun else
242*4882a593Smuzhiyun return 0;
243*4882a593Smuzhiyun }
244*4882a593Smuzhiyun
fan53555_regulator_get_voltage(struct udevice * dev)245*4882a593Smuzhiyun static int fan53555_regulator_get_voltage(struct udevice *dev)
246*4882a593Smuzhiyun {
247*4882a593Smuzhiyun struct fan53555_regulator_info *priv = dev_get_priv(dev);
248*4882a593Smuzhiyun int uvolt = 0, val;
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun val = fan53555_reg_read(dev, priv->vol_reg);
251*4882a593Smuzhiyun val &= priv->vol_mask;
252*4882a593Smuzhiyun uvolt = (val * priv->vsel_step) + priv->vsel_min;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun return uvolt;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun
fan53555_regulator_set_voltage(struct udevice * dev,int uvolt)257*4882a593Smuzhiyun static int fan53555_regulator_set_voltage(struct udevice *dev, int uvolt)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun struct fan53555_regulator_info *priv = dev_get_priv(dev);
260*4882a593Smuzhiyun int val;
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun val = ((uvolt - priv->vsel_min) / priv->vsel_step);
263*4882a593Smuzhiyun fan53555_clrsetbits(dev, priv->vol_reg, priv->vol_mask, val);
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun return 0;
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun
fan53555_regulator_get_suspend_voltage(struct udevice * dev)268*4882a593Smuzhiyun static int fan53555_regulator_get_suspend_voltage(struct udevice *dev)
269*4882a593Smuzhiyun {
270*4882a593Smuzhiyun struct fan53555_regulator_info *priv = dev_get_priv(dev);
271*4882a593Smuzhiyun int uvolt = 0, val;
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun val = fan53555_reg_read(dev, priv->sleep_reg);
274*4882a593Smuzhiyun val &= priv->vol_mask;
275*4882a593Smuzhiyun uvolt = (val * priv->vsel_step) + priv->vsel_min;
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun return uvolt;
278*4882a593Smuzhiyun }
279*4882a593Smuzhiyun
fan53555_regulator_set_suspend_voltage(struct udevice * dev,int uvolt)280*4882a593Smuzhiyun static int fan53555_regulator_set_suspend_voltage(struct udevice *dev,
281*4882a593Smuzhiyun int uvolt)
282*4882a593Smuzhiyun {
283*4882a593Smuzhiyun struct fan53555_regulator_info *priv = dev_get_priv(dev);
284*4882a593Smuzhiyun int val;
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun val = ((uvolt - priv->vsel_min) / priv->vsel_step);
287*4882a593Smuzhiyun fan53555_clrsetbits(dev, priv->sleep_reg, priv->vol_mask, val);
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun return 0;
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun
fan53555_voltages_setup_fairchild(struct fan53555_regulator_info * di)292*4882a593Smuzhiyun static int fan53555_voltages_setup_fairchild(struct fan53555_regulator_info *di)
293*4882a593Smuzhiyun {
294*4882a593Smuzhiyun /* Init voltage range and step */
295*4882a593Smuzhiyun switch (di->chip_id) {
296*4882a593Smuzhiyun case FAN53555_CHIP_ID_00:
297*4882a593Smuzhiyun switch (di->chip_rev) {
298*4882a593Smuzhiyun case FAN53555_CHIP_REV_00:
299*4882a593Smuzhiyun di->vsel_min = 600000;
300*4882a593Smuzhiyun di->vsel_step = 10000;
301*4882a593Smuzhiyun break;
302*4882a593Smuzhiyun case FAN53555_CHIP_REV_13:
303*4882a593Smuzhiyun di->vsel_min = 800000;
304*4882a593Smuzhiyun di->vsel_step = 10000;
305*4882a593Smuzhiyun break;
306*4882a593Smuzhiyun default:
307*4882a593Smuzhiyun dev_err(di->dev,
308*4882a593Smuzhiyun "Chip ID %d with rev %d not supported!\n",
309*4882a593Smuzhiyun di->chip_id, di->chip_rev);
310*4882a593Smuzhiyun return -EINVAL;
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun break;
313*4882a593Smuzhiyun case FAN53555_CHIP_ID_01:
314*4882a593Smuzhiyun case FAN53555_CHIP_ID_03:
315*4882a593Smuzhiyun case FAN53555_CHIP_ID_05:
316*4882a593Smuzhiyun case FAN53555_CHIP_ID_08:
317*4882a593Smuzhiyun di->vsel_min = 600000;
318*4882a593Smuzhiyun di->vsel_step = 10000;
319*4882a593Smuzhiyun break;
320*4882a593Smuzhiyun case FAN53555_CHIP_ID_04:
321*4882a593Smuzhiyun di->vsel_min = 603000;
322*4882a593Smuzhiyun di->vsel_step = 12826;
323*4882a593Smuzhiyun break;
324*4882a593Smuzhiyun default:
325*4882a593Smuzhiyun dev_err(di->dev,
326*4882a593Smuzhiyun "Chip ID %d not supported!\n", di->chip_id);
327*4882a593Smuzhiyun return -EINVAL;
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun di->vol_mask = VSEL_NSEL_MASK;
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun return 0;
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun
fan53555_voltages_setup_silergy(struct fan53555_regulator_info * di)334*4882a593Smuzhiyun static int fan53555_voltages_setup_silergy(struct fan53555_regulator_info *di)
335*4882a593Smuzhiyun {
336*4882a593Smuzhiyun /* Init voltage range and step */
337*4882a593Smuzhiyun di->vsel_min = 712500;
338*4882a593Smuzhiyun di->vsel_step = 12500;
339*4882a593Smuzhiyun di->vol_mask = VSEL_NSEL_MASK;
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun return 0;
342*4882a593Smuzhiyun }
343*4882a593Smuzhiyun
fan53555_voltages_setup_tcs(struct fan53555_regulator_info * di)344*4882a593Smuzhiyun static int fan53555_voltages_setup_tcs(struct fan53555_regulator_info *di)
345*4882a593Smuzhiyun {
346*4882a593Smuzhiyun if (di->sleep_vsel_id) {
347*4882a593Smuzhiyun di->sleep_reg = TCS452X_VSEL1;
348*4882a593Smuzhiyun di->vol_reg = TCS452X_VSEL0;
349*4882a593Smuzhiyun } else {
350*4882a593Smuzhiyun di->sleep_reg = TCS452X_VSEL0;
351*4882a593Smuzhiyun di->vol_reg = TCS452X_VSEL1;
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun di->vol_mask = TCS_VSEL_NSEL_MASK;
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun /* Init voltage range and step */
357*4882a593Smuzhiyun di->vsel_min = 600000;
358*4882a593Smuzhiyun di->vsel_step = 6250;
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun return 0;
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun /* For 00,01,03,05 options:
364*4882a593Smuzhiyun * VOUT = 0.60V + NSELx * 10mV, from 0.60 to 1.23V.
365*4882a593Smuzhiyun * For 04 option:
366*4882a593Smuzhiyun * VOUT = 0.603V + NSELx * 12.826mV, from 0.603 to 1.411V.
367*4882a593Smuzhiyun *
368*4882a593Smuzhiyun */
369*4882a593Smuzhiyun
fan53555_device_setup(struct fan53555_regulator_info * di)370*4882a593Smuzhiyun static int fan53555_device_setup(struct fan53555_regulator_info *di)
371*4882a593Smuzhiyun {
372*4882a593Smuzhiyun int ret = 0;
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun /* Setup voltage control register */
375*4882a593Smuzhiyun switch (di->sleep_vsel_id) {
376*4882a593Smuzhiyun case FAN53555_VSEL_ID_0:
377*4882a593Smuzhiyun di->sleep_reg = FAN53555_VSEL0;
378*4882a593Smuzhiyun di->vol_reg = FAN53555_VSEL1;
379*4882a593Smuzhiyun break;
380*4882a593Smuzhiyun case FAN53555_VSEL_ID_1:
381*4882a593Smuzhiyun di->sleep_reg = FAN53555_VSEL1;
382*4882a593Smuzhiyun di->vol_reg = FAN53555_VSEL0;
383*4882a593Smuzhiyun break;
384*4882a593Smuzhiyun default:
385*4882a593Smuzhiyun dev_err(di->dev, "Invalid VSEL ID!\n");
386*4882a593Smuzhiyun return -EINVAL;
387*4882a593Smuzhiyun }
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun switch (di->vendor) {
390*4882a593Smuzhiyun case FAN53555_VENDOR_FAIRCHILD:
391*4882a593Smuzhiyun ret = fan53555_voltages_setup_fairchild(di);
392*4882a593Smuzhiyun break;
393*4882a593Smuzhiyun case FAN53555_VENDOR_SILERGY:
394*4882a593Smuzhiyun ret = fan53555_voltages_setup_silergy(di);
395*4882a593Smuzhiyun break;
396*4882a593Smuzhiyun case FAN53555_VENDOR_TCS:
397*4882a593Smuzhiyun ret = fan53555_voltages_setup_tcs(di);
398*4882a593Smuzhiyun break;
399*4882a593Smuzhiyun default:
400*4882a593Smuzhiyun dev_err(di->dev, "vendor %d not supported!\n", di->vendor);
401*4882a593Smuzhiyun return -EINVAL;
402*4882a593Smuzhiyun }
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun return ret;
405*4882a593Smuzhiyun }
406*4882a593Smuzhiyun
fan53555_regulator_ofdata_to_platdata(struct udevice * dev)407*4882a593Smuzhiyun static int fan53555_regulator_ofdata_to_platdata(struct udevice *dev)
408*4882a593Smuzhiyun {
409*4882a593Smuzhiyun struct fan53555_regulator_info *priv = dev_get_priv(dev);
410*4882a593Smuzhiyun int ret;
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun priv->sleep_vsel_id = dev_read_u32_default(dev,
413*4882a593Smuzhiyun "fcs,suspend-voltage-selector",
414*4882a593Smuzhiyun 1);
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun ret = gpio_request_by_name(dev, "vsel-gpios", 0,
417*4882a593Smuzhiyun &priv->vsel_gpio, GPIOD_IS_OUT);
418*4882a593Smuzhiyun if (ret)
419*4882a593Smuzhiyun dev_err(dev, "vsel-gpios- not found! Error: %d\n", ret);
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun if (dm_gpio_is_valid(&priv->vsel_gpio))
422*4882a593Smuzhiyun dm_gpio_set_value(&priv->vsel_gpio, !priv->sleep_vsel_id);
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun priv->vendor = dev_get_driver_data(dev);
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun return 0;
427*4882a593Smuzhiyun }
428*4882a593Smuzhiyun
fan53555_regulator_probe(struct udevice * dev)429*4882a593Smuzhiyun static int fan53555_regulator_probe(struct udevice *dev)
430*4882a593Smuzhiyun {
431*4882a593Smuzhiyun struct fan53555_regulator_info *di = dev_get_priv(dev);
432*4882a593Smuzhiyun struct dm_regulator_uclass_platdata *uc_pdata;
433*4882a593Smuzhiyun u8 val;
434*4882a593Smuzhiyun int ret;
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun uc_pdata = dev_get_uclass_platdata(dev);
437*4882a593Smuzhiyun uc_pdata->type = REGULATOR_TYPE_BUCK;
438*4882a593Smuzhiyun uc_pdata->mode_count = 0;
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun /* Get chip ID */
441*4882a593Smuzhiyun val = fan53555_reg_read(dev, FAN53555_ID1);
442*4882a593Smuzhiyun if (val < 0) {
443*4882a593Smuzhiyun dev_err(dev, "Failed to get chip ID!\n");
444*4882a593Smuzhiyun return val;
445*4882a593Smuzhiyun }
446*4882a593Smuzhiyun di->chip_id = val & DIE_ID;
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun /* Get chip revision */
449*4882a593Smuzhiyun val = fan53555_reg_read(dev, FAN53555_ID2);
450*4882a593Smuzhiyun if (val < 0) {
451*4882a593Smuzhiyun dev_err(dev, "Failed to get chip Rev!\n");
452*4882a593Smuzhiyun return val;
453*4882a593Smuzhiyun }
454*4882a593Smuzhiyun di->chip_rev = val & DIE_REV;
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun debug("FAN53555 Option[%d] Rev[%d] Detected!\n",
457*4882a593Smuzhiyun di->chip_id, di->chip_rev);
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun /* Device init */
460*4882a593Smuzhiyun ret = fan53555_device_setup(di);
461*4882a593Smuzhiyun if (ret < 0) {
462*4882a593Smuzhiyun dev_err(dev, "Failed to setup device!\n");
463*4882a593Smuzhiyun return ret;
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun return 0;
467*4882a593Smuzhiyun }
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun static const struct udevice_id fan53555_id[] = {
470*4882a593Smuzhiyun {
471*4882a593Smuzhiyun .compatible = "fan53555",
472*4882a593Smuzhiyun .data = FAN53555_VENDOR_FAIRCHILD,
473*4882a593Smuzhiyun }, {
474*4882a593Smuzhiyun .compatible = "silergy,syr827",
475*4882a593Smuzhiyun .data = FAN53555_VENDOR_SILERGY,
476*4882a593Smuzhiyun }, {
477*4882a593Smuzhiyun .compatible = "silergy,syr828",
478*4882a593Smuzhiyun .data = FAN53555_VENDOR_SILERGY,
479*4882a593Smuzhiyun }, {
480*4882a593Smuzhiyun .compatible = "tcs,tcs452x", /* tcs4525/4526 */
481*4882a593Smuzhiyun .data = FAN53555_VENDOR_TCS,
482*4882a593Smuzhiyun },
483*4882a593Smuzhiyun { },
484*4882a593Smuzhiyun };
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun static const struct dm_regulator_ops fan53555_regulator_ops = {
487*4882a593Smuzhiyun .get_value = fan53555_regulator_get_voltage,
488*4882a593Smuzhiyun .set_value = fan53555_regulator_set_voltage,
489*4882a593Smuzhiyun .set_suspend_value = fan53555_regulator_set_suspend_voltage,
490*4882a593Smuzhiyun .get_suspend_value = fan53555_regulator_get_suspend_voltage,
491*4882a593Smuzhiyun .set_enable = fan53555_regulator_set_enable,
492*4882a593Smuzhiyun .get_enable = fan53555_regulator_get_enable,
493*4882a593Smuzhiyun .set_suspend_enable = fan53555_regulator_set_suspend_enable,
494*4882a593Smuzhiyun .get_suspend_enable = fan53555_regulator_get_suspend_enable,
495*4882a593Smuzhiyun };
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun U_BOOT_DRIVER(fan53555_regulator) = {
498*4882a593Smuzhiyun .name = "fan53555_regulator",
499*4882a593Smuzhiyun .id = UCLASS_REGULATOR,
500*4882a593Smuzhiyun .ops = &fan53555_regulator_ops,
501*4882a593Smuzhiyun .probe = fan53555_regulator_probe,
502*4882a593Smuzhiyun .of_match = fan53555_id,
503*4882a593Smuzhiyun .ofdata_to_platdata = fan53555_regulator_ofdata_to_platdata,
504*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct fan53555_regulator_info),
505*4882a593Smuzhiyun };
506*4882a593Smuzhiyun
507