1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2015 Google, Inc
3*4882a593Smuzhiyun * Written by Simon Glass <sjg@chromium.org>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Based on Rockchip's drivers/power/pmic/pmic_act8846.c:
6*4882a593Smuzhiyun * Copyright (C) 2012 rockchips
7*4882a593Smuzhiyun * zyw <zyw@rock-chips.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun #include <dm.h>
14*4882a593Smuzhiyun #include <errno.h>
15*4882a593Smuzhiyun #include <power/act8846_pmic.h>
16*4882a593Smuzhiyun #include <power/pmic.h>
17*4882a593Smuzhiyun #include <power/regulator.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun static const u16 voltage_map[] = {
20*4882a593Smuzhiyun 600, 625, 650, 675, 700, 725, 750, 775,
21*4882a593Smuzhiyun 800, 825, 850, 875, 900, 925, 950, 975,
22*4882a593Smuzhiyun 1000, 1025, 1050, 1075, 1100, 1125, 1150, 1175,
23*4882a593Smuzhiyun 1200, 1250, 1300, 1350, 1400, 1450, 1500, 1550,
24*4882a593Smuzhiyun 1600, 1650, 1700, 1750, 1800, 1850, 1900, 1950,
25*4882a593Smuzhiyun 2000, 2050, 2100, 2150, 2200, 2250, 2300, 2350,
26*4882a593Smuzhiyun 2400, 2500, 2600, 2700, 2800, 2900, 3000, 3100,
27*4882a593Smuzhiyun 3200, 3300, 3400, 3500, 3600, 3700, 3800, 3900,
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun enum {
31*4882a593Smuzhiyun REG_SYS0,
32*4882a593Smuzhiyun REG_SYS1,
33*4882a593Smuzhiyun REG1_VOL = 0x10,
34*4882a593Smuzhiyun REG1_CTL = 0X11,
35*4882a593Smuzhiyun REG2_VOL0 = 0x20,
36*4882a593Smuzhiyun REG2_VOL1,
37*4882a593Smuzhiyun REG2_CTL,
38*4882a593Smuzhiyun REG3_VOL0 = 0x30,
39*4882a593Smuzhiyun REG3_VOL1,
40*4882a593Smuzhiyun REG3_CTL,
41*4882a593Smuzhiyun REG4_VOL0 = 0x40,
42*4882a593Smuzhiyun REG4_VOL1,
43*4882a593Smuzhiyun REG4_CTL,
44*4882a593Smuzhiyun REG5_VOL = 0x50,
45*4882a593Smuzhiyun REG5_CTL,
46*4882a593Smuzhiyun REG6_VOL = 0X58,
47*4882a593Smuzhiyun REG6_CTL,
48*4882a593Smuzhiyun REG7_VOL = 0x60,
49*4882a593Smuzhiyun REG7_CTL,
50*4882a593Smuzhiyun REG8_VOL = 0x68,
51*4882a593Smuzhiyun REG8_CTL,
52*4882a593Smuzhiyun REG9_VOL = 0x70,
53*4882a593Smuzhiyun REG9_CTL,
54*4882a593Smuzhiyun REG10_VOL = 0x80,
55*4882a593Smuzhiyun REG10_CTL,
56*4882a593Smuzhiyun REG11_VOL = 0x90,
57*4882a593Smuzhiyun REG11_CTL,
58*4882a593Smuzhiyun REG12_VOL = 0xa0,
59*4882a593Smuzhiyun REG12_CTL,
60*4882a593Smuzhiyun REG13 = 0xb1,
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun static const u8 addr_vol[] = {
64*4882a593Smuzhiyun 0, REG1_VOL, REG2_VOL0, REG3_VOL0, REG4_VOL0,
65*4882a593Smuzhiyun REG5_VOL, REG6_VOL, REG7_VOL, REG8_VOL, REG9_VOL,
66*4882a593Smuzhiyun REG10_VOL, REG11_VOL, REG12_VOL,
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun static const u8 addr_ctl[] = {
70*4882a593Smuzhiyun 0, REG1_CTL, REG2_CTL, REG3_CTL, REG4_CTL,
71*4882a593Smuzhiyun REG5_CTL, REG6_CTL, REG7_CTL, REG8_CTL, REG9_CTL,
72*4882a593Smuzhiyun REG10_CTL, REG11_CTL, REG12_CTL,
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun
check_volt_table(const u16 * volt_table,int uvolt)75*4882a593Smuzhiyun static int check_volt_table(const u16 *volt_table, int uvolt)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun int i;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun for (i = VOL_MIN_IDX; i < VOL_MAX_IDX; i++) {
80*4882a593Smuzhiyun if (uvolt <= (volt_table[i] * 1000))
81*4882a593Smuzhiyun return i;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun return -EINVAL;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
reg_get_value(struct udevice * dev)86*4882a593Smuzhiyun static int reg_get_value(struct udevice *dev)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun int reg = dev->driver_data;
89*4882a593Smuzhiyun int ret;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun ret = pmic_reg_read(dev->parent, addr_vol[reg]);
92*4882a593Smuzhiyun if (ret < 0)
93*4882a593Smuzhiyun return ret;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun return voltage_map[ret & LDO_VOL_MASK] * 1000;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
reg_set_value(struct udevice * dev,int uvolt)98*4882a593Smuzhiyun static int reg_set_value(struct udevice *dev, int uvolt)
99*4882a593Smuzhiyun {
100*4882a593Smuzhiyun int reg = dev->driver_data;
101*4882a593Smuzhiyun int val;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun val = check_volt_table(voltage_map, uvolt);
104*4882a593Smuzhiyun if (val < 0)
105*4882a593Smuzhiyun return val;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun return pmic_clrsetbits(dev->parent, addr_vol[reg], LDO_VOL_MASK, val);
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
reg_set_enable(struct udevice * dev,bool enable)110*4882a593Smuzhiyun static int reg_set_enable(struct udevice *dev, bool enable)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun int reg = dev->driver_data;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun return pmic_clrsetbits(dev->parent, addr_ctl[reg], LDO_EN_MASK,
115*4882a593Smuzhiyun enable ? LDO_EN_MASK : 0);
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
reg_get_enable(struct udevice * dev)118*4882a593Smuzhiyun static int reg_get_enable(struct udevice *dev)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun int reg = dev->driver_data;
121*4882a593Smuzhiyun int ret;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun ret = pmic_reg_read(dev->parent, addr_ctl[reg]);
124*4882a593Smuzhiyun if (ret < 0)
125*4882a593Smuzhiyun return ret;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun return ret & LDO_EN_MASK ? true : false;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
act8846_reg_probe(struct udevice * dev)130*4882a593Smuzhiyun static int act8846_reg_probe(struct udevice *dev)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun struct dm_regulator_uclass_platdata *uc_pdata;
133*4882a593Smuzhiyun int reg = dev->driver_data;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun uc_pdata = dev_get_uclass_platdata(dev);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun uc_pdata->type = reg <= 4 ? REGULATOR_TYPE_BUCK : REGULATOR_TYPE_LDO;
138*4882a593Smuzhiyun uc_pdata->mode_count = 0;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun return 0;
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun static const struct dm_regulator_ops act8846_reg_ops = {
144*4882a593Smuzhiyun .get_value = reg_get_value,
145*4882a593Smuzhiyun .set_value = reg_set_value,
146*4882a593Smuzhiyun .get_enable = reg_get_enable,
147*4882a593Smuzhiyun .set_enable = reg_set_enable,
148*4882a593Smuzhiyun };
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun U_BOOT_DRIVER(act8846_buck) = {
151*4882a593Smuzhiyun .name = "act8846_reg",
152*4882a593Smuzhiyun .id = UCLASS_REGULATOR,
153*4882a593Smuzhiyun .ops = &act8846_reg_ops,
154*4882a593Smuzhiyun .probe = act8846_reg_probe,
155*4882a593Smuzhiyun };
156