1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2015-2017 Google, Inc 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * USB Type-C Port Controller Interface. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __LINUX_USB_TCPCI_H 9*4882a593Smuzhiyun #define __LINUX_USB_TCPCI_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define TCPC_VENDOR_ID 0x0 12*4882a593Smuzhiyun #define TCPC_PRODUCT_ID 0x2 13*4882a593Smuzhiyun #define TCPC_BCD_DEV 0x4 14*4882a593Smuzhiyun #define TCPC_TC_REV 0x6 15*4882a593Smuzhiyun #define TCPC_PD_REV 0x8 16*4882a593Smuzhiyun #define TCPC_PD_INT_REV 0xa 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define TCPC_ALERT 0x10 19*4882a593Smuzhiyun #define TCPC_ALERT_VBUS_DISCNCT BIT(11) 20*4882a593Smuzhiyun #define TCPC_ALERT_RX_BUF_OVF BIT(10) 21*4882a593Smuzhiyun #define TCPC_ALERT_FAULT BIT(9) 22*4882a593Smuzhiyun #define TCPC_ALERT_V_ALARM_LO BIT(8) 23*4882a593Smuzhiyun #define TCPC_ALERT_V_ALARM_HI BIT(7) 24*4882a593Smuzhiyun #define TCPC_ALERT_TX_SUCCESS BIT(6) 25*4882a593Smuzhiyun #define TCPC_ALERT_TX_DISCARDED BIT(5) 26*4882a593Smuzhiyun #define TCPC_ALERT_TX_FAILED BIT(4) 27*4882a593Smuzhiyun #define TCPC_ALERT_RX_HARD_RST BIT(3) 28*4882a593Smuzhiyun #define TCPC_ALERT_RX_STATUS BIT(2) 29*4882a593Smuzhiyun #define TCPC_ALERT_POWER_STATUS BIT(1) 30*4882a593Smuzhiyun #define TCPC_ALERT_CC_STATUS BIT(0) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define TCPC_ALERT_MASK 0x12 33*4882a593Smuzhiyun #define TCPC_POWER_STATUS_MASK 0x14 34*4882a593Smuzhiyun #define TCPC_FAULT_STATUS_MASK 0x15 35*4882a593Smuzhiyun #define TCPC_CONFIG_STD_OUTPUT 0x18 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define TCPC_TCPC_CTRL 0x19 38*4882a593Smuzhiyun #define TCPC_TCPC_CTRL_ORIENTATION BIT(0) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define TCPC_ROLE_CTRL 0x1a 41*4882a593Smuzhiyun #define TCPC_ROLE_CTRL_DRP BIT(6) 42*4882a593Smuzhiyun #define TCPC_ROLE_CTRL_RP_VAL_SHIFT 4 43*4882a593Smuzhiyun #define TCPC_ROLE_CTRL_RP_VAL_MASK 0x3 44*4882a593Smuzhiyun #define TCPC_ROLE_CTRL_RP_VAL_DEF 0x0 45*4882a593Smuzhiyun #define TCPC_ROLE_CTRL_RP_VAL_1_5 0x1 46*4882a593Smuzhiyun #define TCPC_ROLE_CTRL_RP_VAL_3_0 0x2 47*4882a593Smuzhiyun #define TCPC_ROLE_CTRL_CC2_SHIFT 2 48*4882a593Smuzhiyun #define TCPC_ROLE_CTRL_CC2_MASK 0x3 49*4882a593Smuzhiyun #define TCPC_ROLE_CTRL_CC1_SHIFT 0 50*4882a593Smuzhiyun #define TCPC_ROLE_CTRL_CC1_MASK 0x3 51*4882a593Smuzhiyun #define TCPC_ROLE_CTRL_CC_RA 0x0 52*4882a593Smuzhiyun #define TCPC_ROLE_CTRL_CC_RP 0x1 53*4882a593Smuzhiyun #define TCPC_ROLE_CTRL_CC_RD 0x2 54*4882a593Smuzhiyun #define TCPC_ROLE_CTRL_CC_OPEN 0x3 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define TCPC_FAULT_CTRL 0x1b 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define TCPC_POWER_CTRL 0x1c 59*4882a593Smuzhiyun #define TCPC_POWER_CTRL_VCONN_ENABLE BIT(0) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define TCPC_CC_STATUS 0x1d 62*4882a593Smuzhiyun #define TCPC_CC_STATUS_TOGGLING BIT(5) 63*4882a593Smuzhiyun #define TCPC_CC_STATUS_TERM BIT(4) 64*4882a593Smuzhiyun #define TCPC_CC_STATUS_CC2_SHIFT 2 65*4882a593Smuzhiyun #define TCPC_CC_STATUS_CC2_MASK 0x3 66*4882a593Smuzhiyun #define TCPC_CC_STATUS_CC1_SHIFT 0 67*4882a593Smuzhiyun #define TCPC_CC_STATUS_CC1_MASK 0x3 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define TCPC_POWER_STATUS 0x1e 70*4882a593Smuzhiyun #define TCPC_POWER_STATUS_UNINIT BIT(6) 71*4882a593Smuzhiyun #define TCPC_POWER_STATUS_VBUS_DET BIT(3) 72*4882a593Smuzhiyun #define TCPC_POWER_STATUS_VBUS_PRES BIT(2) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define TCPC_FAULT_STATUS 0x1f 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define TCPC_COMMAND 0x23 77*4882a593Smuzhiyun #define TCPC_CMD_WAKE_I2C 0x11 78*4882a593Smuzhiyun #define TCPC_CMD_DISABLE_VBUS_DETECT 0x22 79*4882a593Smuzhiyun #define TCPC_CMD_ENABLE_VBUS_DETECT 0x33 80*4882a593Smuzhiyun #define TCPC_CMD_DISABLE_SINK_VBUS 0x44 81*4882a593Smuzhiyun #define TCPC_CMD_SINK_VBUS 0x55 82*4882a593Smuzhiyun #define TCPC_CMD_DISABLE_SRC_VBUS 0x66 83*4882a593Smuzhiyun #define TCPC_CMD_SRC_VBUS_DEFAULT 0x77 84*4882a593Smuzhiyun #define TCPC_CMD_SRC_VBUS_HIGH 0x88 85*4882a593Smuzhiyun #define TCPC_CMD_LOOK4CONNECTION 0x99 86*4882a593Smuzhiyun #define TCPC_CMD_RXONEMORE 0xAA 87*4882a593Smuzhiyun #define TCPC_CMD_I2C_IDLE 0xFF 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define TCPC_DEV_CAP_1 0x24 90*4882a593Smuzhiyun #define TCPC_DEV_CAP_2 0x26 91*4882a593Smuzhiyun #define TCPC_STD_INPUT_CAP 0x28 92*4882a593Smuzhiyun #define TCPC_STD_OUTPUT_CAP 0x29 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define TCPC_MSG_HDR_INFO 0x2e 95*4882a593Smuzhiyun #define TCPC_MSG_HDR_INFO_DATA_ROLE BIT(3) 96*4882a593Smuzhiyun #define TCPC_MSG_HDR_INFO_PWR_ROLE BIT(0) 97*4882a593Smuzhiyun #define TCPC_MSG_HDR_INFO_REV_SHIFT 1 98*4882a593Smuzhiyun #define TCPC_MSG_HDR_INFO_REV_MASK 0x3 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define TCPC_RX_DETECT 0x2f 101*4882a593Smuzhiyun #define TCPC_RX_DETECT_HARD_RESET BIT(5) 102*4882a593Smuzhiyun #define TCPC_RX_DETECT_SOP BIT(0) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define TCPC_RX_BYTE_CNT 0x30 105*4882a593Smuzhiyun #define TCPC_RX_BUF_FRAME_TYPE 0x31 106*4882a593Smuzhiyun #define TCPC_RX_HDR 0x32 107*4882a593Smuzhiyun #define TCPC_RX_DATA 0x34 /* through 0x4f */ 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define TCPC_TRANSMIT 0x50 110*4882a593Smuzhiyun #define TCPC_TRANSMIT_RETRY_SHIFT 4 111*4882a593Smuzhiyun #define TCPC_TRANSMIT_RETRY_MASK 0x3 112*4882a593Smuzhiyun #define TCPC_TRANSMIT_TYPE_SHIFT 0 113*4882a593Smuzhiyun #define TCPC_TRANSMIT_TYPE_MASK 0x7 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define TCPC_TX_BYTE_CNT 0x51 116*4882a593Smuzhiyun #define TCPC_TX_HDR 0x52 117*4882a593Smuzhiyun #define TCPC_TX_DATA 0x54 /* through 0x6f */ 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define TCPC_VBUS_VOLTAGE 0x70 120*4882a593Smuzhiyun #define TCPC_VBUS_SINK_DISCONNECT_THRESH 0x72 121*4882a593Smuzhiyun #define TCPC_VBUS_STOP_DISCHARGE_THRESH 0x74 122*4882a593Smuzhiyun #define TCPC_VBUS_VOLTAGE_ALARM_HI_CFG 0x76 123*4882a593Smuzhiyun #define TCPC_VBUS_VOLTAGE_ALARM_LO_CFG 0x78 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun #define TCPC_BMCIO_CTRL 0x90 126*4882a593Smuzhiyun #define TCPC_BMCIO_VBUS_DETECT_MASK BIT(1) 127*4882a593Smuzhiyun #define TCPC_BMCIO_VBUS_DETECT_ENABLE BIT(1) 128*4882a593Smuzhiyun #define TCPC_BMCIO_VBUS_DETECT_DISABLE 0 129*4882a593Smuzhiyun #define TCPC_BMCIO_24M_OSC_MASK BIT(0) 130*4882a593Smuzhiyun #define TCPC_BMCIO_ENABLE_24M_OSC BIT(0) 131*4882a593Smuzhiyun #define TCPC_BMCIO_DISABLE_24M_OSC 0 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun struct tcpci; 134*4882a593Smuzhiyun struct tcpci_data { 135*4882a593Smuzhiyun struct regmap *regmap; 136*4882a593Smuzhiyun int (*init)(struct tcpci *tcpci, struct tcpci_data *data); 137*4882a593Smuzhiyun int (*set_vconn)(struct tcpci *tcpci, struct tcpci_data *data, 138*4882a593Smuzhiyun bool enable); 139*4882a593Smuzhiyun int (*start_drp_toggling)(struct tcpci *tcpci, struct tcpci_data *data, 140*4882a593Smuzhiyun enum typec_cc_status cc); 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun struct tcpci *tcpci_register_port(struct udevice *dev, struct tcpci_data *data); 144*4882a593Smuzhiyun void tcpci_unregister_port(struct tcpci *tcpci); 145*4882a593Smuzhiyun int tcpci_get_voltage_fun(struct tcpci *tcpci); 146*4882a593Smuzhiyun int tcpci_get_current_fun(struct tcpci *tcpci); 147*4882a593Smuzhiyun int tcpci_get_online_fun(struct tcpci *tcpci); 148*4882a593Smuzhiyun irqreturn_t tcpci_irq(struct tcpci *tcpci); 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun #endif /* __LINUX_USB_TCPCI_H */ 151