1 /*
2 **Copyright (C) 2021 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <errno.h>
10 #include <irq-generic.h>
11 #include <power/rk8xx_pmic.h>
12 #include <power/pmic.h>
13 #include <spi.h>
14
15 DECLARE_GLOBAL_DATA_PTR;
16
17 #define RK806_CHIP_NAME 0x5A
18 #define RK806_CHIP_VER 0x5B
19 #define RK806_HW_VER 0x21
20 #define HW_DUAL_PMIC 0x28
21 #define HW_SINGLE_PMIC 0xe8
22
23 #define RK806_CMD_READ 0
24 #define RK806_CMD_WRITE BIT(7)
25 #define RK806_CMD_CRC_EN BIT(6)
26 #define RK806_CMD_CRC_DIS 0
27 #define RK806_CMD_LEN_MSK 0x0f
28 #define RK806_REG_H 0x00
29
30 #define RK806_SYS_CFG1 0x5f
31 #define RK806_PWRCTRL_CONFIG0 0x62
32 #define RK806_PWRCTRL_CONFIG1 0x63
33 #define RK806_VSEL_CTR_SEL0 0x64
34 #define RK806_DVS_CTR_SEL4 0x6e
35 #define RK806_SYS_CFG3 0x72
36 #define RK806_PWRON_KEY 0x76
37 #define RK806_INT_STS0 0x77
38 #define RK806_INT_MSK0 0x78
39 #define RK806_INT_STS1 0x79
40 #define RK806_INT_MSK1 0x7A
41 #define RK806_GPIO_INT_CONFIG 0x7B
42 #define RK806_ON_SOURCE 0xf4
43 #define RK806_OFF_SOURCE 0xf5
44
45 #define RK806_IRQ_PWRON_FALL_MSK BIT(0)
46 #define RK806_IRQ_PWRON_RISE_MSK BIT(1)
47 #define RK806_DEV_OFF BIT(0)
48 #define RK806_RST_MODE1 0x01
49 #define RK806_RST_MODE2 0x02
50 #define RK806_PWRCTRL_FUN_MSK 0x88
51 #define RK806_VSEL_CTRL_MSK 0xcc
52 #define RK806_VSEL_PWRCTRL1 0x11
53 #define RK806_ENABLE_PWRCTRL 0x04
54 #define VERSION_AB 0x01
55
56 #if CONFIG_IS_ENABLED(IRQ)
57 /* RK805 */
58 static const struct virq_reg rk806_irqs[] = {
59 [RK8XX_IRQ_PWRON_FALL] = {
60 .mask = RK806_IRQ_PWRON_FALL_MSK,
61 .reg_offset = 0,
62 },
63 [RK8XX_IRQ_PWRON_RISE] = {
64 .mask = RK806_IRQ_PWRON_RISE_MSK,
65 .reg_offset = 0,
66 },
67 };
68
69 static struct virq_chip rk806_irq_chip = {
70 .status_base = RK806_INT_STS0,
71 .mask_base = RK806_INT_MSK0,
72 .num_regs = 1,
73 .read = pmic_reg_read,
74 .write = pmic_reg_write,
75 .irqs = rk806_irqs,
76 .num_irqs = ARRAY_SIZE(rk806_irqs),
77 };
78 #endif
79
80 static const struct pmic_child_info pmic_children_info[] = {
81 { .prefix = "DCDC", .driver = "rk8xx_spi_buck"},
82 { .prefix = "NLDO", .driver = "rk8xx_spi_ldo"},
83 { .prefix = "PLDO", .driver = "rk8xx_spi_pldo"},
84 { },
85 };
86
87 static const struct pmic_child_info power_key_info[] = {
88 { .prefix = "pwrkey", .driver = "rk8xx_pwrkey"},
89 { },
90 };
91
_spi_read(struct udevice * dev,u32 reg,u8 * buffer,int len)92 static int _spi_read(struct udevice *dev, u32 reg, u8 *buffer, int len)
93 {
94 struct rk8xx_priv *priv = dev_get_priv(dev);
95 u8 txbuf[3];
96 int ret;
97
98 if (spi_claim_bus(priv->slave))
99 return -EBUSY;
100
101 txbuf[0] = RK806_CMD_READ;
102 txbuf[1] = reg;
103 txbuf[2] = RK806_REG_H;
104
105 ret = spi_write_then_read(priv->slave, txbuf, 3, NULL, buffer, 1);
106 spi_release_bus(priv->slave);
107
108 return ret;
109 }
110
_spi_write(struct udevice * dev,uint reg,const u8 * buffer,int len)111 static int _spi_write(struct udevice *dev, uint reg, const u8 *buffer, int len)
112 {
113 struct rk8xx_priv *priv = dev_get_priv(dev);
114 u8 txbuf[4];
115 int ret;
116
117 if (len < 1) {
118 dev_err(dev, "rk806 write error: len < 1\n");
119 return -EINVAL;
120 }
121
122 if (spi_claim_bus(priv->slave))
123 return -EBUSY;
124
125 txbuf[0] = RK806_CMD_WRITE;
126 txbuf[1] = reg;
127 txbuf[2] = RK806_REG_H;
128 txbuf[3] = *buffer;
129
130 ret = spi_write_then_read(priv->slave, txbuf, 4, NULL, NULL, 0);
131 spi_release_bus(priv->slave);
132
133 return ret;
134 }
135
rk806_spi_read(struct udevice * dev,uint reg,u8 * buffer,int len)136 static int rk806_spi_read(struct udevice *dev,
137 uint reg,
138 u8 *buffer,
139 int len)
140 {
141 int ret;
142
143 ret = _spi_read(dev, reg, buffer, len);
144 if (ret)
145 dev_err(dev, "rk806 read reg(0x%x) error: %d\n", reg, ret);
146
147 return ret;
148 }
149
rk806_spi_write(struct udevice * dev,uint reg,const u8 * buffer,int len)150 static int rk806_spi_write(struct udevice *dev,
151 uint reg,
152 const u8 *buffer,
153 int len)
154 {
155 int ret;
156
157 ret = _spi_write(dev, reg, buffer, len);
158 if (ret)
159 dev_err(dev, "rk806 write reg(0x%x) error: %d\n", reg, ret);
160
161 return ret;
162 }
163
rk8xx_spi_reg_count(struct udevice * dev)164 static int rk8xx_spi_reg_count(struct udevice *dev)
165 {
166 return 0xff;
167 }
168
169 #if CONFIG_IS_ENABLED(PMIC_CHILDREN)
rk8xx_spi_bind(struct udevice * dev)170 static int rk8xx_spi_bind(struct udevice *dev)
171 {
172 ofnode regulators_node;
173 int children;
174
175 regulators_node = dev_read_subnode(dev, "regulators");
176 if (!ofnode_valid(regulators_node)) {
177 debug("%s: %s regulators subnode not found!\n", __func__,
178 dev->name);
179 return -ENXIO;
180 }
181
182 children = pmic_bind_children(dev, regulators_node, pmic_children_info);
183 if (!children)
184 debug("%s: %s - no child found\n", __func__, dev->name);
185
186 children = pmic_bind_children(dev, dev->node, power_key_info);
187 if (!children)
188 debug("%s: %s - no child found\n", __func__, dev->name);
189
190 return 0;
191 }
192 #endif
193 #if CONFIG_IS_ENABLED(IRQ)
rk8xx_spi_ofdata_to_platdata(struct udevice * dev)194 static int rk8xx_spi_ofdata_to_platdata(struct udevice *dev)
195 {
196 struct rk8xx_priv *rk8xx = dev_get_priv(dev);
197 u32 interrupt, phandle;
198 int ret;
199
200 rk8xx->rst_fun = dev_read_u32_default(dev, "pmic-reset-func", 0);
201
202 phandle = dev_read_u32_default(dev, "interrupt-parent", -ENODATA);
203 if (phandle == -ENODATA) {
204 printf("Read 'interrupt-parent' failed, ret=%d\n", phandle);
205 return phandle;
206 }
207
208 ret = dev_read_u32_array(dev, "interrupts", &interrupt, 1);
209 if (ret) {
210 printf("Read 'interrupts' failed, ret=%d\n", ret);
211 return ret;
212 }
213
214 rk8xx->irq = phandle_gpio_to_irq(phandle, interrupt);
215 if (rk8xx->irq < 0)
216 printf("Failed to request rk8xx irq, ret=%d\n", rk8xx->irq);
217
218 return 0;
219 }
220
rk8xx_spi_irq_chip_init(struct udevice * dev)221 static int rk8xx_spi_irq_chip_init(struct udevice *dev)
222 {
223 struct rk8xx_priv *priv = dev_get_priv(dev);
224 struct virq_chip *irq_chip = NULL;
225 u8 value;
226 int ret;
227
228 value = 0xff;
229 rk806_spi_write(dev, RK806_INT_STS0, &value, 1);
230 rk806_spi_write(dev, RK806_INT_STS1, &value, 1);
231 rk806_spi_write(dev, RK806_INT_MSK0, &value, 1);
232 rk806_spi_write(dev, RK806_INT_MSK1, &value, 1);
233 value = 0x00;
234 rk806_spi_write(dev, RK806_GPIO_INT_CONFIG, &value, 1);
235
236 irq_chip = &rk806_irq_chip;
237
238 if (irq_chip && priv->irq > 0) {
239 ret = virq_add_chip(dev, irq_chip, priv->irq);
240 if (ret) {
241 printf("Failed to add irqchip(irq=%d), ret=%d\n",
242 priv->irq, ret);
243 return ret;
244 }
245 priv->irq_chip = irq_chip;
246 }
247
248 return 0;
249 }
250 #else
rk8xx_spi_ofdata_to_platdata(struct udevice * dev)251 static inline int rk8xx_spi_ofdata_to_platdata(struct udevice *dev)
252 {
253 return 0;
254 }
255
rk8xx_spi_irq_chip_init(struct udevice * dev)256 static inline int rk8xx_spi_irq_chip_init(struct udevice *dev)
257 {
258 return 0;
259 }
260 #endif
261
rk8xx_spi_probe(struct udevice * dev)262 static int rk8xx_spi_probe(struct udevice *dev)
263 {
264 struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
265 struct rk8xx_priv *priv = dev_get_priv(dev);
266 struct udevice *spi = dev_get_parent(dev);
267 struct spi_slave *slave = NULL;
268 u8 on_source, off_source;
269 u8 msb, lsb, value = 0;
270 int ret;
271
272 if (spi->seq < 0) {
273 dev_err(dev, "Failed to configure the spi num\n");
274 return -EINVAL;
275 }
276
277 slave = spi_setup_slave(spi->seq, plat->cs, plat->max_hz,
278 plat->mode);
279 if (!slave)
280 return -ENODEV;
281 priv->slave = slave;
282
283 /* read Chip variant */
284 ret = rk806_spi_read(dev, RK806_CHIP_NAME, &msb, 1);
285 if (ret) {
286 dev_err(dev, "rk806 name read error: %d\n", ret);
287 return ret;
288 }
289
290 ret = rk806_spi_read(dev, RK806_CHIP_VER, &lsb, 1);
291 if (ret) {
292 dev_err(dev, "rk806 version read error: %d\n", ret);
293 return ret;
294 }
295
296 priv->variant = ((msb << 8) | lsb) & RK8XX_ID_MSK;
297 printf("spi%d: RK%x%x: %d\n", spi->seq, msb, (lsb >> 4), lsb & 0x0f);
298
299 rk806_spi_read(dev, RK806_ON_SOURCE, &on_source, 1);
300 rk806_spi_read(dev, RK806_OFF_SOURCE, &off_source, 1);
301 printf("ON=0x%02x, OFF=0x%02x\n", on_source, off_source);
302
303 ret = rk806_spi_read(dev, RK806_HW_VER, &value, 1);
304 if (ret)
305 panic("RK806: read RK806_HW_VER error!\n");
306 /* dual rk806 dev name: "rk806master@0", "rk806slave@1"
307 * single rk806 dev name: " rk806single@0"
308 */
309 if ((!strcmp(dev->name, "rk806master@0")) || (!strcmp(dev->name, "rk806slave@1"))) {
310 if (value != HW_DUAL_PMIC) {
311 dev_err(dev, "HW single pmic, the firmware dual pmic(0x%x)!\n", value);
312 run_command("download", 0);
313 }
314 } else {
315 if (value != HW_SINGLE_PMIC) {
316 dev_err(dev, "HW dual pmic, the firmware single pmic(0x%x)!\n", value);
317 run_command("download", 0);
318 }
319 }
320
321 if ((lsb & 0x0f) == VERSION_AB) {
322 ret = rk806_spi_read(dev, RK806_SYS_CFG1, &value, 1);
323 if (ret) {
324 dev_err(dev, "rk806 RK806_SYS_CFG1 read error: %d\n", ret);
325 return ret;
326 }
327 value |= 0x80;
328 rk806_spi_write(dev, RK806_SYS_CFG1, &value, 1);
329 }
330
331 if (priv->rst_fun) {
332 rk806_spi_read(dev, RK806_SYS_CFG3, &value, 1);
333 value &= 0x3f;
334 if (priv->rst_fun == RK806_RST_MODE1) {
335 value |= (RK806_RST_MODE1 << 6);
336 rk806_spi_write(dev, RK806_SYS_CFG3, &value, 1);
337 } else if (priv->rst_fun == RK806_RST_MODE2) {
338 value |= (RK806_RST_MODE2 << 6);
339 rk806_spi_write(dev, RK806_SYS_CFG3, &value, 1);
340 }
341 }
342
343 rk8xx_spi_irq_chip_init(dev);
344
345 return 0;
346 }
347
rk8xx_spi_shutdown(struct udevice * dev)348 static int rk8xx_spi_shutdown(struct udevice *dev)
349 {
350 u8 dev_off;
351 int ret = 0;
352
353 ret = rk806_spi_read(dev, RK806_SYS_CFG3, &dev_off, 1);
354 if (ret)
355 return ret;
356
357 dev_off |= RK806_DEV_OFF;
358 ret = rk806_spi_write(dev, RK806_SYS_CFG3, &dev_off, 1);
359 if (ret) {
360 dev_err(dev, "rk806 shutdown error: %d\n", ret);
361 return ret;
362 }
363
364 while (1)
365 ;
366
367 return 0;
368 }
369
rk806_suspend(struct udevice * dev)370 static int rk806_suspend(struct udevice *dev)
371 {
372 int ret = 0;
373 u8 i, val;
374
375 ret = rk806_spi_read(dev, RK806_PWRCTRL_CONFIG0, &val, 1);
376 if (ret)
377 return ret;
378 val &= RK806_PWRCTRL_FUN_MSK;
379 ret = rk806_spi_write(dev, RK806_PWRCTRL_CONFIG0, &val, 1);
380 if (ret)
381 return ret;
382
383 ret = rk806_spi_read(dev, RK806_PWRCTRL_CONFIG1, &val, 1);
384 if (ret)
385 return ret;
386 val &= RK806_PWRCTRL_FUN_MSK;
387 ret = rk806_spi_write(dev, RK806_PWRCTRL_CONFIG1, &val, 1);
388 if (ret)
389 return ret;
390
391 for (i = RK806_VSEL_CTR_SEL0; i <= 0x6e; i++) {
392 ret = rk806_spi_read(dev, i, &val, 1);
393 if (ret)
394 return ret;
395 val &= RK806_VSEL_CTRL_MSK;
396 ret = rk806_spi_write(dev, i, &val, 1);
397 if (ret)
398 return ret;
399 }
400
401 ret = rk806_spi_read(dev, RK806_PWRCTRL_CONFIG0, &val, 1);
402 if (ret)
403 return ret;
404 val &= RK806_PWRCTRL_FUN_MSK;
405 val |= RK806_ENABLE_PWRCTRL;
406 ret = rk806_spi_write(dev, RK806_PWRCTRL_CONFIG0, &val, 1);
407 if (ret)
408 return ret;
409
410 for (i = RK806_VSEL_CTR_SEL0; i <= RK806_DVS_CTR_SEL4; i++) {
411 ret = rk806_spi_read(dev, i, &val, 1);
412 if (ret)
413 return ret;
414 val &= RK806_VSEL_CTRL_MSK;
415 val |= RK806_VSEL_PWRCTRL1;
416 ret = rk806_spi_write(dev, i, &val, 1);
417 if (ret)
418 return ret;
419 }
420
421 return ret;
422 }
423
rk806_resume(struct udevice * dev)424 static int rk806_resume(struct udevice *dev)
425 {
426 int ret = 0;
427 u8 i, val;
428
429 for (i = RK806_VSEL_CTR_SEL0; i <= RK806_DVS_CTR_SEL4; i++) {
430 ret = rk806_spi_read(dev, i, &val, 1);
431 if (ret)
432 return ret;
433 val &= RK806_VSEL_CTRL_MSK;
434 ret = rk806_spi_write(dev, i, &val, 1);
435 if (ret)
436 return ret;
437 }
438
439 ret = rk806_spi_read(dev, RK806_PWRCTRL_CONFIG0, &val, 1);
440 if (ret)
441 return ret;
442 val &= RK806_PWRCTRL_FUN_MSK;
443 ret = rk806_spi_write(dev, RK806_PWRCTRL_CONFIG0, &val, 1);
444 if (ret)
445 return ret;
446
447 ret = rk806_spi_read(dev, RK806_PWRCTRL_CONFIG1, &val, 1);
448 if (ret)
449 return ret;
450 val &= RK806_PWRCTRL_FUN_MSK;
451 ret = rk806_spi_write(dev, RK806_PWRCTRL_CONFIG1, &val, 1);
452 if (ret)
453 return ret;
454
455 return ret;
456 }
457
458 static struct dm_pmic_ops rk8xx_spi_ops = {
459 .reg_count = rk8xx_spi_reg_count,
460 .read = rk806_spi_read,
461 .write = rk806_spi_write,
462 .shutdown = rk8xx_spi_shutdown,
463 .suspend = rk806_suspend,
464 .resume = rk806_resume,
465 };
466
467 static const struct udevice_id rk8xx_spi_ids[] = {
468 { .compatible = "rockchip,rk806" },
469 { }
470 };
471
472 U_BOOT_DRIVER(pmic_rk8xx_spi) = {
473 .name = "rk806-pmic",
474 .id = UCLASS_PMIC,
475 .of_match = rk8xx_spi_ids,
476 #if CONFIG_IS_ENABLED(PMIC_CHILDREN)
477 .bind = rk8xx_spi_bind,
478 #endif
479 .ofdata_to_platdata = rk8xx_spi_ofdata_to_platdata,
480 .priv_auto_alloc_size = sizeof(struct rk8xx_priv),
481 .probe = rk8xx_spi_probe,
482 .ops = &rk8xx_spi_ops,
483 };
484