1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2015 Linaro
3*4882a593Smuzhiyun * Peter Griffin <peter.griffin@linaro.org>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #include <asm/io.h>
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <power/pmic.h>
10*4882a593Smuzhiyun #include <power/max8997_muic.h>
11*4882a593Smuzhiyun #include <power/hi6553_pmic.h>
12*4882a593Smuzhiyun #include <errno.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun u8 *pmussi_base;
15*4882a593Smuzhiyun
hi6553_readb(u32 offset)16*4882a593Smuzhiyun uint8_t hi6553_readb(u32 offset)
17*4882a593Smuzhiyun {
18*4882a593Smuzhiyun return readb(pmussi_base + (offset << 2));
19*4882a593Smuzhiyun }
20*4882a593Smuzhiyun
hi6553_writeb(u32 offset,uint8_t value)21*4882a593Smuzhiyun void hi6553_writeb(u32 offset, uint8_t value)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun writeb(value, pmussi_base + (offset << 2));
24*4882a593Smuzhiyun }
25*4882a593Smuzhiyun
pmic_reg_write(struct pmic * p,u32 reg,u32 val)26*4882a593Smuzhiyun int pmic_reg_write(struct pmic *p, u32 reg, u32 val)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun if (check_reg(p, reg))
29*4882a593Smuzhiyun return -EINVAL;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun hi6553_writeb(reg, (uint8_t)val);
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun return 0;
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
pmic_reg_read(struct pmic * p,u32 reg,u32 * val)36*4882a593Smuzhiyun int pmic_reg_read(struct pmic *p, u32 reg, u32 *val)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun if (check_reg(p, reg))
39*4882a593Smuzhiyun return -EINVAL;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun *val = (u32)hi6553_readb(reg);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun return 0;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
hi6553_init(void)46*4882a593Smuzhiyun static void hi6553_init(void)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun int data;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun hi6553_writeb(HI6553_PERI_EN_MARK, 0x1e);
51*4882a593Smuzhiyun hi6553_writeb(HI6553_NP_REG_ADJ1, 0);
52*4882a593Smuzhiyun data = HI6553_DISABLE6_XO_CLK_CONN | HI6553_DISABLE6_XO_CLK_NFC |
53*4882a593Smuzhiyun HI6553_DISABLE6_XO_CLK_RF1 | HI6553_DISABLE6_XO_CLK_RF2;
54*4882a593Smuzhiyun hi6553_writeb(HI6553_DISABLE6_XO_CLK, data);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* configure BUCK0 & BUCK1 */
57*4882a593Smuzhiyun hi6553_writeb(HI6553_BUCK01_CTRL2, 0x5e);
58*4882a593Smuzhiyun hi6553_writeb(HI6553_BUCK0_CTRL7, 0x10);
59*4882a593Smuzhiyun hi6553_writeb(HI6553_BUCK1_CTRL7, 0x10);
60*4882a593Smuzhiyun hi6553_writeb(HI6553_BUCK0_CTRL5, 0x1e);
61*4882a593Smuzhiyun hi6553_writeb(HI6553_BUCK1_CTRL5, 0x1e);
62*4882a593Smuzhiyun hi6553_writeb(HI6553_BUCK0_CTRL1, 0xfc);
63*4882a593Smuzhiyun hi6553_writeb(HI6553_BUCK1_CTRL1, 0xfc);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* configure BUCK2 */
66*4882a593Smuzhiyun hi6553_writeb(HI6553_BUCK2_REG1, 0x4f);
67*4882a593Smuzhiyun hi6553_writeb(HI6553_BUCK2_REG5, 0x99);
68*4882a593Smuzhiyun hi6553_writeb(HI6553_BUCK2_REG6, 0x45);
69*4882a593Smuzhiyun mdelay(1);
70*4882a593Smuzhiyun hi6553_writeb(HI6553_VSET_BUCK2_ADJ, 0x22);
71*4882a593Smuzhiyun mdelay(1);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /* configure BUCK3 */
74*4882a593Smuzhiyun hi6553_writeb(HI6553_BUCK3_REG3, 0x02);
75*4882a593Smuzhiyun hi6553_writeb(HI6553_BUCK3_REG5, 0x99);
76*4882a593Smuzhiyun hi6553_writeb(HI6553_BUCK3_REG6, 0x41);
77*4882a593Smuzhiyun hi6553_writeb(HI6553_VSET_BUCK3_ADJ, 0x02);
78*4882a593Smuzhiyun mdelay(1);
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /* configure BUCK4 */
81*4882a593Smuzhiyun hi6553_writeb(HI6553_BUCK4_REG2, 0x9a);
82*4882a593Smuzhiyun hi6553_writeb(HI6553_BUCK4_REG5, 0x99);
83*4882a593Smuzhiyun hi6553_writeb(HI6553_BUCK4_REG6, 0x45);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /* configure LDO20 */
86*4882a593Smuzhiyun hi6553_writeb(HI6553_LDO20_REG_ADJ, 0x50);
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun hi6553_writeb(HI6553_NP_REG_CHG, 0x0f);
89*4882a593Smuzhiyun hi6553_writeb(HI6553_CLK_TOP0, 0x06);
90*4882a593Smuzhiyun hi6553_writeb(HI6553_CLK_TOP3, 0xc0);
91*4882a593Smuzhiyun hi6553_writeb(HI6553_CLK_TOP4, 0x00);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun /* configure LDO7 & LDO10 for SD slot */
94*4882a593Smuzhiyun data = hi6553_readb(HI6553_LDO7_REG_ADJ);
95*4882a593Smuzhiyun data = (data & 0xf8) | 0x2;
96*4882a593Smuzhiyun hi6553_writeb(HI6553_LDO7_REG_ADJ, data);
97*4882a593Smuzhiyun mdelay(5);
98*4882a593Smuzhiyun /* enable LDO7 */
99*4882a593Smuzhiyun hi6553_writeb(HI6553_ENABLE2_LDO1_8, 1 << 6);
100*4882a593Smuzhiyun mdelay(5);
101*4882a593Smuzhiyun data = hi6553_readb(HI6553_LDO10_REG_ADJ);
102*4882a593Smuzhiyun data = (data & 0xf8) | 0x5;
103*4882a593Smuzhiyun hi6553_writeb(HI6553_LDO10_REG_ADJ, data);
104*4882a593Smuzhiyun mdelay(5);
105*4882a593Smuzhiyun /* enable LDO10 */
106*4882a593Smuzhiyun hi6553_writeb(HI6553_ENABLE3_LDO9_16, 1 << 1);
107*4882a593Smuzhiyun mdelay(5);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* select 32.764KHz */
110*4882a593Smuzhiyun hi6553_writeb(HI6553_CLK19M2_600_586_EN, 0x01);
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
power_hi6553_init(u8 * base)113*4882a593Smuzhiyun int power_hi6553_init(u8 *base)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun static const char name[] = "HI6553 PMIC";
116*4882a593Smuzhiyun struct pmic *p = pmic_alloc();
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun if (!p) {
119*4882a593Smuzhiyun printf("%s: POWER allocation error!\n", __func__);
120*4882a593Smuzhiyun return -ENOMEM;
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun p->name = name;
124*4882a593Smuzhiyun p->interface = PMIC_NONE;
125*4882a593Smuzhiyun p->number_of_regs = 44;
126*4882a593Smuzhiyun pmussi_base = base;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun hi6553_init();
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun puts("HI6553 PMIC init\n");
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun return 0;
133*4882a593Smuzhiyun }
134