1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _FG_RK8XX_H_ 8*4882a593Smuzhiyun #define _FG_RK8XX_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* register definition */ 11*4882a593Smuzhiyun #define SECONDS_REG 0X00 12*4882a593Smuzhiyun #define VB_MON_REG 0x21 13*4882a593Smuzhiyun #define THERMAL_REG 0x22 14*4882a593Smuzhiyun #define SUP_STS_REG 0xA0 15*4882a593Smuzhiyun #define USB_CTRL_REG 0xA1 16*4882a593Smuzhiyun #define CHRG_CTRL_REG1 0xA3 17*4882a593Smuzhiyun #define CHRG_CTRL_REG2 0xA4 18*4882a593Smuzhiyun #define CHRG_CTRL_REG3 0xA5 19*4882a593Smuzhiyun #define BAT_CTRL_REG 0xA6 20*4882a593Smuzhiyun #define BAT_HTS_TS_REG 0xA8 21*4882a593Smuzhiyun #define BAT_LTS_TS_REG 0xA9 22*4882a593Smuzhiyun #define TS_CTRL_REG 0xAC 23*4882a593Smuzhiyun #define ADC_CTRL_REG 0xAD 24*4882a593Smuzhiyun #define GGCON_REG 0xB0 25*4882a593Smuzhiyun #define GGSTS_REG 0xB1 26*4882a593Smuzhiyun #define ZERO_CUR_ADC_REGH 0xB2 27*4882a593Smuzhiyun #define ZERO_CUR_ADC_REGL 0xB3 28*4882a593Smuzhiyun #define GASCNT_CAL_REG3 0xB4 29*4882a593Smuzhiyun #define GASCNT_CAL_REG2 0xB5 30*4882a593Smuzhiyun #define GASCNT_CAL_REG1 0xB6 31*4882a593Smuzhiyun #define GASCNT_CAL_REG0 0xB7 32*4882a593Smuzhiyun #define GASCNT_REG3 0xB8 33*4882a593Smuzhiyun #define GASCNT_REG2 0xB9 34*4882a593Smuzhiyun #define GASCNT_REG1 0xBA 35*4882a593Smuzhiyun #define GASCNT_REG0 0xBB 36*4882a593Smuzhiyun #define BAT_CUR_AVG_REGH 0xBC 37*4882a593Smuzhiyun #define BAT_CUR_AVG_REGL 0xBD 38*4882a593Smuzhiyun #define TS_ADC_REGH 0xBE 39*4882a593Smuzhiyun #define TS_ADC_REGL 0xBF 40*4882a593Smuzhiyun #define RK818_TS2_ADC_REGH 0xC0 41*4882a593Smuzhiyun #define RK818_TS2_ADC_REGL 0xC1 42*4882a593Smuzhiyun #define RK816_USB_ADC_REGH 0xC0 43*4882a593Smuzhiyun #define RK816_USB_ADC_REGL 0xC1 44*4882a593Smuzhiyun #define BAT_OCV_REGH 0xC2 45*4882a593Smuzhiyun #define BAT_OCV_REGL 0xC3 46*4882a593Smuzhiyun #define BAT_VOL_REGH 0xC4 47*4882a593Smuzhiyun #define BAT_VOL_REGL 0xC5 48*4882a593Smuzhiyun #define RELAX_ENTRY_THRES_REGH 0xC6 49*4882a593Smuzhiyun #define RELAX_ENTRY_THRES_REGL 0xC7 50*4882a593Smuzhiyun #define RELAX_EXIT_THRES_REGH 0xC8 51*4882a593Smuzhiyun #define RELAX_EXIT_THRES_REGL 0xC9 52*4882a593Smuzhiyun #define RELAX_VOL1_REGH 0xCA 53*4882a593Smuzhiyun #define RELAX_VOL1_REGL 0xCB 54*4882a593Smuzhiyun #define RELAX_VOL2_REGH 0xCC 55*4882a593Smuzhiyun #define RELAX_VOL2_REGL 0xCD 56*4882a593Smuzhiyun #define RELAX_CUR1_REGH 0xCE 57*4882a593Smuzhiyun #define RELAX_CUR1_REGL 0xCF 58*4882a593Smuzhiyun #define RELAX_CUR2_REGH 0xD0 59*4882a593Smuzhiyun #define RELAX_CUR2_REGL 0xD1 60*4882a593Smuzhiyun #define CAL_OFFSET_REGH 0xD2 61*4882a593Smuzhiyun #define CAL_OFFSET_REGL 0xD3 62*4882a593Smuzhiyun #define NON_ACT_TIMER_CNT_REG 0xD4 63*4882a593Smuzhiyun #define VCALIB0_REGH 0xD5 64*4882a593Smuzhiyun #define VCALIB0_REGL 0xD6 65*4882a593Smuzhiyun #define VCALIB1_REGH 0xD7 66*4882a593Smuzhiyun #define VCALIB1_REGL 0xD8 67*4882a593Smuzhiyun #define FCC_GASCNT_REG3 0xD9 68*4882a593Smuzhiyun #define FCC_GASCNT_REG2 0xDA 69*4882a593Smuzhiyun #define FCC_GASCNT_REG1 0xDB 70*4882a593Smuzhiyun #define FCC_GASCNT_REG0 0xDC 71*4882a593Smuzhiyun #define IOFFSET_REGH 0xDD 72*4882a593Smuzhiyun #define IOFFSET_REGL 0xDE 73*4882a593Smuzhiyun #define SLEEP_CON_SAMP_CUR_REG 0xDF 74*4882a593Smuzhiyun #define SOC_REG 0xE0 75*4882a593Smuzhiyun #define REMAIN_CAP_REG3 0xE1 76*4882a593Smuzhiyun #define REMAIN_CAP_REG2 0xE2 77*4882a593Smuzhiyun #define REMAIN_CAP_REG1 0xE3 78*4882a593Smuzhiyun #define REMAIN_CAP_REG0 0xE4 79*4882a593Smuzhiyun #define UPDAT_LEVE_REG 0xE5 80*4882a593Smuzhiyun #define NEW_FCC_REG3 0xE6 81*4882a593Smuzhiyun #define NEW_FCC_REG2 0xE7 82*4882a593Smuzhiyun #define NEW_FCC_REG1 0xE8 83*4882a593Smuzhiyun #define NEW_FCC_REG0 0xE9 84*4882a593Smuzhiyun #define NON_ACT_TIMER_CNT_SAVE_REG 0xEA 85*4882a593Smuzhiyun #define OCV_VOL_VALID_REG 0xEB 86*4882a593Smuzhiyun #define REBOOT_CNT_REG 0xEC 87*4882a593Smuzhiyun #define POFFSET_REG 0xED 88*4882a593Smuzhiyun #define MISC_MARK_REG 0xEE 89*4882a593Smuzhiyun #define HALT_CNT_REG 0xEF 90*4882a593Smuzhiyun #define DATA15_REG 0xEF 91*4882a593Smuzhiyun #define DATA16_REG 0xF0 92*4882a593Smuzhiyun #define DATA17_REG 0xF1 93*4882a593Smuzhiyun #define DATA18_REG 0xF2 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #endif 96