1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2009 Faraday Technology 3*4882a593Smuzhiyun * Po-Yu Chuang <ratbert@faraday-tech.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2010 Andes Technology Corporation 6*4882a593Smuzhiyun * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 7*4882a593Smuzhiyun * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <common.h> 13*4882a593Smuzhiyun #include <asm/io.h> 14*4882a593Smuzhiyun #include <faraday/ftpmu010.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* OSCC: OSC Control Register */ ftpmu010_32768osc_enable(void)17*4882a593Smuzhiyunvoid ftpmu010_32768osc_enable(void) 18*4882a593Smuzhiyun { 19*4882a593Smuzhiyun static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; 20*4882a593Smuzhiyun unsigned int oscc; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* enable the 32768Hz oscillator */ 23*4882a593Smuzhiyun oscc = readl(&pmu->OSCC); 24*4882a593Smuzhiyun oscc &= ~(FTPMU010_OSCC_OSCL_OFF | FTPMU010_OSCC_OSCL_TRI); 25*4882a593Smuzhiyun writel(oscc, &pmu->OSCC); 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* wait until ready */ 28*4882a593Smuzhiyun while (!(readl(&pmu->OSCC) & FTPMU010_OSCC_OSCL_STABLE)) 29*4882a593Smuzhiyun ; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* select 32768Hz oscillator */ 32*4882a593Smuzhiyun oscc = readl(&pmu->OSCC); 33*4882a593Smuzhiyun oscc |= FTPMU010_OSCC_OSCL_RTCLSEL; 34*4882a593Smuzhiyun writel(oscc, &pmu->OSCC); 35*4882a593Smuzhiyun } 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* MFPSR: Multi-Function Port Setting Register */ ftpmu010_mfpsr_select_dev(unsigned int dev)38*4882a593Smuzhiyunvoid ftpmu010_mfpsr_select_dev(unsigned int dev) 39*4882a593Smuzhiyun { 40*4882a593Smuzhiyun static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; 41*4882a593Smuzhiyun unsigned int mfpsr; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun mfpsr = readl(&pmu->MFPSR); 44*4882a593Smuzhiyun mfpsr |= dev; 45*4882a593Smuzhiyun writel(mfpsr, &pmu->MFPSR); 46*4882a593Smuzhiyun } 47*4882a593Smuzhiyun ftpmu010_mfpsr_diselect_dev(unsigned int dev)48*4882a593Smuzhiyunvoid ftpmu010_mfpsr_diselect_dev(unsigned int dev) 49*4882a593Smuzhiyun { 50*4882a593Smuzhiyun static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; 51*4882a593Smuzhiyun unsigned int mfpsr; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun mfpsr = readl(&pmu->MFPSR); 54*4882a593Smuzhiyun mfpsr &= ~dev; 55*4882a593Smuzhiyun writel(mfpsr, &pmu->MFPSR); 56*4882a593Smuzhiyun } 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* PDLLCR0: PLL/DLL Control Register 0 */ ftpmu010_dlldis_disable(void)59*4882a593Smuzhiyunvoid ftpmu010_dlldis_disable(void) 60*4882a593Smuzhiyun { 61*4882a593Smuzhiyun static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; 62*4882a593Smuzhiyun unsigned int pdllcr0; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun pdllcr0 = readl(&pmu->PDLLCR0); 65*4882a593Smuzhiyun pdllcr0 |= FTPMU010_PDLLCR0_DLLDIS; 66*4882a593Smuzhiyun writel(pdllcr0, &pmu->PDLLCR0); 67*4882a593Smuzhiyun } 68*4882a593Smuzhiyun ftpmu010_sdram_clk_disable(unsigned int cr0)69*4882a593Smuzhiyunvoid ftpmu010_sdram_clk_disable(unsigned int cr0) 70*4882a593Smuzhiyun { 71*4882a593Smuzhiyun static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; 72*4882a593Smuzhiyun unsigned int pdllcr0; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun pdllcr0 = readl(&pmu->PDLLCR0); 75*4882a593Smuzhiyun pdllcr0 |= FTPMU010_PDLLCR0_HCLKOUTDIS(cr0); 76*4882a593Smuzhiyun writel(pdllcr0, &pmu->PDLLCR0); 77*4882a593Smuzhiyun } 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* SDRAMHTC: SDRAM Signal Hold Time Control */ ftpmu010_sdramhtc_set(unsigned int val)80*4882a593Smuzhiyunvoid ftpmu010_sdramhtc_set(unsigned int val) 81*4882a593Smuzhiyun { 82*4882a593Smuzhiyun static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; 83*4882a593Smuzhiyun unsigned int sdramhtc; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun sdramhtc = readl(&pmu->SDRAMHTC); 86*4882a593Smuzhiyun sdramhtc |= val; 87*4882a593Smuzhiyun writel(sdramhtc, &pmu->SDRAMHTC); 88*4882a593Smuzhiyun } 89