1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2015-2016 Socionext Inc. 3*4882a593Smuzhiyun * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __PINCTRL_UNIPHIER_H__ 9*4882a593Smuzhiyun #define __PINCTRL_UNIPHIER_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/bitops.h> 12*4882a593Smuzhiyun #include <linux/bug.h> 13*4882a593Smuzhiyun #include <linux/kernel.h> 14*4882a593Smuzhiyun #include <linux/types.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define UNIPHIER_PIN_ATTR_PACKED(iectrl) (iectrl) 17*4882a593Smuzhiyun uniphier_pin_get_iectrl(unsigned long data)18*4882a593Smuzhiyunstatic inline unsigned int uniphier_pin_get_iectrl(unsigned long data) 19*4882a593Smuzhiyun { 20*4882a593Smuzhiyun return data; 21*4882a593Smuzhiyun } 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /** 24*4882a593Smuzhiyun * struct uniphier_pinctrl_pin - pin data for UniPhier SoC 25*4882a593Smuzhiyun * 26*4882a593Smuzhiyun * @number: pin number 27*4882a593Smuzhiyun * @data: additional per-pin data 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun struct uniphier_pinctrl_pin { 30*4882a593Smuzhiyun unsigned number; 31*4882a593Smuzhiyun unsigned long data; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /** 35*4882a593Smuzhiyun * struct uniphier_pinctrl_group - pin group data for UniPhier SoC 36*4882a593Smuzhiyun * 37*4882a593Smuzhiyun * @name: pin group name 38*4882a593Smuzhiyun * @pins: array of pins that belong to the group 39*4882a593Smuzhiyun * @num_pins: number of pins in the group 40*4882a593Smuzhiyun * @muxvals: array of values to be set to pinmux registers 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun struct uniphier_pinctrl_group { 43*4882a593Smuzhiyun const char *name; 44*4882a593Smuzhiyun const unsigned *pins; 45*4882a593Smuzhiyun unsigned num_pins; 46*4882a593Smuzhiyun const int *muxvals; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /** 50*4882a593Smuzhiyun * struct uniphier_pinctrl_socdata - SoC data for UniPhier pin controller 51*4882a593Smuzhiyun * 52*4882a593Smuzhiyun * @pins: array of pin data 53*4882a593Smuzhiyun * @pins_count: number of pin data 54*4882a593Smuzhiyun * @groups: array of pin group data 55*4882a593Smuzhiyun * @groups_count: number of pin group data 56*4882a593Smuzhiyun * @functions: array of pinmux function names 57*4882a593Smuzhiyun * @functions_count: number of pinmux functions 58*4882a593Smuzhiyun * @mux_bits: bit width of each pinmux register 59*4882a593Smuzhiyun * @reg_stride: stride of pinmux register address 60*4882a593Smuzhiyun * @caps: SoC-specific capability flag 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun struct uniphier_pinctrl_socdata { 63*4882a593Smuzhiyun const struct uniphier_pinctrl_pin *pins; 64*4882a593Smuzhiyun int pins_count; 65*4882a593Smuzhiyun const struct uniphier_pinctrl_group *groups; 66*4882a593Smuzhiyun int groups_count; 67*4882a593Smuzhiyun const char * const *functions; 68*4882a593Smuzhiyun int functions_count; 69*4882a593Smuzhiyun unsigned caps; 70*4882a593Smuzhiyun #define UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE BIT(3) 71*4882a593Smuzhiyun #define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL BIT(2) 72*4882a593Smuzhiyun #define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(1) 73*4882a593Smuzhiyun #define UNIPHIER_PINCTRL_CAPS_MUX_4BIT BIT(0) 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define UNIPHIER_PINCTRL_PIN(a, b) \ 77*4882a593Smuzhiyun { \ 78*4882a593Smuzhiyun .number = a, \ 79*4882a593Smuzhiyun .data = UNIPHIER_PIN_ATTR_PACKED(b), \ 80*4882a593Smuzhiyun } 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define __UNIPHIER_PINCTRL_GROUP(grp) \ 83*4882a593Smuzhiyun { \ 84*4882a593Smuzhiyun .name = #grp, \ 85*4882a593Smuzhiyun .pins = grp##_pins, \ 86*4882a593Smuzhiyun .num_pins = ARRAY_SIZE(grp##_pins), \ 87*4882a593Smuzhiyun .muxvals = grp##_muxvals + \ 88*4882a593Smuzhiyun BUILD_BUG_ON_ZERO(ARRAY_SIZE(grp##_pins) != \ 89*4882a593Smuzhiyun ARRAY_SIZE(grp##_muxvals)), \ 90*4882a593Smuzhiyun } 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define __UNIPHIER_PINMUX_FUNCTION(func) #func 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD 95*4882a593Smuzhiyun /* 96*4882a593Smuzhiyun * a tricky way to drop unneeded *_pins and *_muxvals arrays from SPL, 97*4882a593Smuzhiyun * suppressing "defined but not used" warnings. 98*4882a593Smuzhiyun */ 99*4882a593Smuzhiyun #define UNIPHIER_PINCTRL_GROUP(grp) \ 100*4882a593Smuzhiyun { .num_pins = ARRAY_SIZE(grp##_pins) + ARRAY_SIZE(grp##_muxvals) } 101*4882a593Smuzhiyun #define UNIPHIER_PINMUX_FUNCTION(func) NULL 102*4882a593Smuzhiyun #else 103*4882a593Smuzhiyun #define UNIPHIER_PINCTRL_GROUP(grp) __UNIPHIER_PINCTRL_GROUP(grp) 104*4882a593Smuzhiyun #define UNIPHIER_PINMUX_FUNCTION(func) __UNIPHIER_PINMUX_FUNCTION(func) 105*4882a593Smuzhiyun #endif 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define UNIPHIER_PINCTRL_GROUP_SPL(grp) __UNIPHIER_PINCTRL_GROUP(grp) 108*4882a593Smuzhiyun #define UNIPHIER_PINMUX_FUNCTION_SPL(func) __UNIPHIER_PINMUX_FUNCTION(func) 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /** 111*4882a593Smuzhiyun * struct uniphier_pinctrl_priv - private data for UniPhier pinctrl driver 112*4882a593Smuzhiyun * 113*4882a593Smuzhiyun * @base: base address of the pinctrl device 114*4882a593Smuzhiyun * @socdata: SoC specific data 115*4882a593Smuzhiyun */ 116*4882a593Smuzhiyun struct uniphier_pinctrl_priv { 117*4882a593Smuzhiyun void __iomem *base; 118*4882a593Smuzhiyun struct uniphier_pinctrl_socdata *socdata; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun extern const struct pinctrl_ops uniphier_pinctrl_ops; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun int uniphier_pinctrl_probe(struct udevice *dev, 124*4882a593Smuzhiyun struct uniphier_pinctrl_socdata *socdata); 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #endif /* __PINCTRL_UNIPHIER_H__ */ 127