1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * (C) Copyright 2019 Rockchip Electronics Co., Ltd
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <common.h>
7*4882a593Smuzhiyun #include <dm.h>
8*4882a593Smuzhiyun #include <dm/pinctrl.h>
9*4882a593Smuzhiyun #include <regmap.h>
10*4882a593Smuzhiyun #include <syscon.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "pinctrl-rockchip.h"
13*4882a593Smuzhiyun
rk3036_set_mux(struct rockchip_pin_bank * bank,int pin,int mux)14*4882a593Smuzhiyun static int rk3036_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
15*4882a593Smuzhiyun {
16*4882a593Smuzhiyun struct rockchip_pinctrl_priv *priv = bank->priv;
17*4882a593Smuzhiyun int iomux_num = (pin / 8);
18*4882a593Smuzhiyun struct regmap *regmap;
19*4882a593Smuzhiyun int reg, ret, mask, mux_type;
20*4882a593Smuzhiyun u8 bit;
21*4882a593Smuzhiyun u32 data;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
24*4882a593Smuzhiyun ? priv->regmap_pmu : priv->regmap_base;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* get basic quadrupel of mux registers and the correct reg inside */
27*4882a593Smuzhiyun mux_type = bank->iomux[iomux_num].type;
28*4882a593Smuzhiyun reg = bank->iomux[iomux_num].offset;
29*4882a593Smuzhiyun reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun data = (mask << (bit + 16));
32*4882a593Smuzhiyun data |= (mux & mask) << bit;
33*4882a593Smuzhiyun ret = regmap_write(regmap, reg, data);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun return ret;
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #define RK3036_PULL_OFFSET 0x118
39*4882a593Smuzhiyun #define RK3036_PULL_PINS_PER_REG 16
40*4882a593Smuzhiyun #define RK3036_PULL_BANK_STRIDE 8
41*4882a593Smuzhiyun
rk3036_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)42*4882a593Smuzhiyun static void rk3036_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
43*4882a593Smuzhiyun int pin_num, struct regmap **regmap,
44*4882a593Smuzhiyun int *reg, u8 *bit)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun struct rockchip_pinctrl_priv *priv = bank->priv;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun *regmap = priv->regmap_base;
49*4882a593Smuzhiyun *reg = RK3036_PULL_OFFSET;
50*4882a593Smuzhiyun *reg += bank->bank_num * RK3036_PULL_BANK_STRIDE;
51*4882a593Smuzhiyun *reg += (pin_num / RK3036_PULL_PINS_PER_REG) * 4;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun *bit = pin_num % RK3036_PULL_PINS_PER_REG;
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun
rk3036_set_pull(struct rockchip_pin_bank * bank,int pin_num,int pull)56*4882a593Smuzhiyun static int rk3036_set_pull(struct rockchip_pin_bank *bank,
57*4882a593Smuzhiyun int pin_num, int pull)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun struct regmap *regmap;
60*4882a593Smuzhiyun int reg, ret;
61*4882a593Smuzhiyun u8 bit;
62*4882a593Smuzhiyun u32 data;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
65*4882a593Smuzhiyun pull != PIN_CONFIG_BIAS_DISABLE)
66*4882a593Smuzhiyun return -ENOTSUPP;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun rk3036_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
69*4882a593Smuzhiyun data = BIT(bit + 16);
70*4882a593Smuzhiyun if (pull == PIN_CONFIG_BIAS_DISABLE)
71*4882a593Smuzhiyun data |= BIT(bit);
72*4882a593Smuzhiyun ret = regmap_write(regmap, reg, data);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun return ret;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun static struct rockchip_pin_bank rk3036_pin_banks[] = {
78*4882a593Smuzhiyun PIN_BANK(0, 32, "gpio0"),
79*4882a593Smuzhiyun PIN_BANK(1, 32, "gpio1"),
80*4882a593Smuzhiyun PIN_BANK(2, 32, "gpio2"),
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
84*4882a593Smuzhiyun .pin_banks = rk3036_pin_banks,
85*4882a593Smuzhiyun .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
86*4882a593Smuzhiyun .nr_pins = 96,
87*4882a593Smuzhiyun .grf_mux_offset = 0xa8,
88*4882a593Smuzhiyun .set_mux = rk3036_set_mux,
89*4882a593Smuzhiyun .set_pull = rk3036_set_pull,
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun static const struct udevice_id rk3036_pinctrl_ids[] = {
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun .compatible = "rockchip,rk3036-pinctrl",
95*4882a593Smuzhiyun .data = (ulong)&rk3036_pin_ctrl
96*4882a593Smuzhiyun },
97*4882a593Smuzhiyun {}
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun U_BOOT_DRIVER(pinctrl_rockchip) = {
101*4882a593Smuzhiyun .name = "rk3036-pinctrl",
102*4882a593Smuzhiyun .id = UCLASS_PINCTRL,
103*4882a593Smuzhiyun .of_match = rk3036_pinctrl_ids,
104*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
105*4882a593Smuzhiyun .ops = &rockchip_pinctrl_ops,
106*4882a593Smuzhiyun #if !CONFIG_IS_ENABLED(OF_PLATDATA)
107*4882a593Smuzhiyun .bind = dm_scan_fdt_dev,
108*4882a593Smuzhiyun #endif
109*4882a593Smuzhiyun .probe = rockchip_pinctrl_probe,
110*4882a593Smuzhiyun };
111