1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Exynos7420 pinctrl driver.
3*4882a593Smuzhiyun * Copyright (C) 2016 Samsung Electronics
4*4882a593Smuzhiyun * Thomas Abraham <thomas.ab@samsung.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <dm.h>
11*4882a593Smuzhiyun #include <errno.h>
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun #include <dm/pinctrl.h>
14*4882a593Smuzhiyun #include <dm/root.h>
15*4882a593Smuzhiyun #include <fdtdec.h>
16*4882a593Smuzhiyun #include <asm/arch/pinmux.h>
17*4882a593Smuzhiyun #include "pinctrl-exynos.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define GPD1_OFFSET 0xc0
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun static struct exynos_pinctrl_config_data serial2_conf[] = {
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun .offset = GPD1_OFFSET + PIN_CON,
26*4882a593Smuzhiyun .mask = 0x00ff0000,
27*4882a593Smuzhiyun .value = 0x00220000,
28*4882a593Smuzhiyun }, {
29*4882a593Smuzhiyun .offset = GPD1_OFFSET + PIN_PUD,
30*4882a593Smuzhiyun .mask = 0x00000f00,
31*4882a593Smuzhiyun .value = 0x00000f00,
32*4882a593Smuzhiyun },
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun
exynos7420_pinctrl_request(struct udevice * dev,int peripheral,int flags)35*4882a593Smuzhiyun static int exynos7420_pinctrl_request(struct udevice *dev, int peripheral,
36*4882a593Smuzhiyun int flags)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun struct exynos_pinctrl_priv *priv = dev_get_priv(dev);
39*4882a593Smuzhiyun unsigned long base = priv->base;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun switch (PERIPH_ID_UART2) {
42*4882a593Smuzhiyun case PERIPH_ID_UART2:
43*4882a593Smuzhiyun exynos_pinctrl_setup_peri(serial2_conf,
44*4882a593Smuzhiyun ARRAY_SIZE(serial2_conf), base);
45*4882a593Smuzhiyun break;
46*4882a593Smuzhiyun default:
47*4882a593Smuzhiyun return -ENODEV;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun return 0;
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun static struct pinctrl_ops exynos7420_pinctrl_ops = {
54*4882a593Smuzhiyun .set_state = exynos_pinctrl_set_state,
55*4882a593Smuzhiyun .request = exynos7420_pinctrl_request,
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* pin banks of Exynos7420 pin-controller - BUS0 */
59*4882a593Smuzhiyun static const struct samsung_pin_bank_data exynos7420_pin_banks0[] = {
60*4882a593Smuzhiyun EXYNOS_PIN_BANK(5, 0x000, "gpb0"),
61*4882a593Smuzhiyun EXYNOS_PIN_BANK(8, 0x020, "gpc0"),
62*4882a593Smuzhiyun EXYNOS_PIN_BANK(2, 0x040, "gpc1"),
63*4882a593Smuzhiyun EXYNOS_PIN_BANK(6, 0x060, "gpc2"),
64*4882a593Smuzhiyun EXYNOS_PIN_BANK(8, 0x080, "gpc3"),
65*4882a593Smuzhiyun EXYNOS_PIN_BANK(4, 0x0a0, "gpd0"),
66*4882a593Smuzhiyun EXYNOS_PIN_BANK(6, 0x0c0, "gpd1"),
67*4882a593Smuzhiyun EXYNOS_PIN_BANK(8, 0x0e0, "gpd2"),
68*4882a593Smuzhiyun EXYNOS_PIN_BANK(5, 0x100, "gpd4"),
69*4882a593Smuzhiyun EXYNOS_PIN_BANK(4, 0x120, "gpd5"),
70*4882a593Smuzhiyun EXYNOS_PIN_BANK(6, 0x140, "gpd6"),
71*4882a593Smuzhiyun EXYNOS_PIN_BANK(3, 0x160, "gpd7"),
72*4882a593Smuzhiyun EXYNOS_PIN_BANK(2, 0x180, "gpd8"),
73*4882a593Smuzhiyun EXYNOS_PIN_BANK(2, 0x1a0, "gpg0"),
74*4882a593Smuzhiyun EXYNOS_PIN_BANK(4, 0x1c0, "gpg3"),
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* pin banks of Exynos7420 pin-controller - FSYS0 */
78*4882a593Smuzhiyun static const struct samsung_pin_bank_data exynos7420_pin_banks1[] = {
79*4882a593Smuzhiyun EXYNOS_PIN_BANK(7, 0x000, "gpr4"),
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* pin banks of Exynos7420 pin-controller - FSYS1 */
83*4882a593Smuzhiyun static const struct samsung_pin_bank_data exynos7420_pin_banks2[] = {
84*4882a593Smuzhiyun EXYNOS_PIN_BANK(4, 0x000, "gpr0"),
85*4882a593Smuzhiyun EXYNOS_PIN_BANK(8, 0x020, "gpr1"),
86*4882a593Smuzhiyun EXYNOS_PIN_BANK(5, 0x040, "gpr2"),
87*4882a593Smuzhiyun EXYNOS_PIN_BANK(8, 0x060, "gpr3"),
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun const struct samsung_pin_ctrl exynos7420_pin_ctrl[] = {
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun /* pin-controller instance BUS0 data */
93*4882a593Smuzhiyun .pin_banks = exynos7420_pin_banks0,
94*4882a593Smuzhiyun .nr_banks = ARRAY_SIZE(exynos7420_pin_banks0),
95*4882a593Smuzhiyun }, {
96*4882a593Smuzhiyun /* pin-controller instance FSYS0 data */
97*4882a593Smuzhiyun .pin_banks = exynos7420_pin_banks1,
98*4882a593Smuzhiyun .nr_banks = ARRAY_SIZE(exynos7420_pin_banks1),
99*4882a593Smuzhiyun }, {
100*4882a593Smuzhiyun /* pin-controller instance FSYS1 data */
101*4882a593Smuzhiyun .pin_banks = exynos7420_pin_banks2,
102*4882a593Smuzhiyun .nr_banks = ARRAY_SIZE(exynos7420_pin_banks2),
103*4882a593Smuzhiyun },
104*4882a593Smuzhiyun };
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun static const struct udevice_id exynos7420_pinctrl_ids[] = {
107*4882a593Smuzhiyun { .compatible = "samsung,exynos7420-pinctrl",
108*4882a593Smuzhiyun .data = (ulong)exynos7420_pin_ctrl },
109*4882a593Smuzhiyun { }
110*4882a593Smuzhiyun };
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun U_BOOT_DRIVER(pinctrl_exynos7420) = {
113*4882a593Smuzhiyun .name = "pinctrl_exynos7420",
114*4882a593Smuzhiyun .id = UCLASS_PINCTRL,
115*4882a593Smuzhiyun .of_match = exynos7420_pinctrl_ids,
116*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct exynos_pinctrl_priv),
117*4882a593Smuzhiyun .ops = &exynos7420_pinctrl_ops,
118*4882a593Smuzhiyun .probe = exynos_pinctrl_probe,
119*4882a593Smuzhiyun .flags = DM_FLAG_PRE_RELOC
120*4882a593Smuzhiyun };
121