1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Exynos pinctrl driver header. 3*4882a593Smuzhiyun * Copyright (C) 2016 Samsung Electronics 4*4882a593Smuzhiyun * Thomas Abraham <thomas.ab@samsung.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __PINCTRL_EXYNOS_H_ 10*4882a593Smuzhiyun #define __PINCTRL_EXYNOS__H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define PIN_CON 0x00 /* Offset of pin function register */ 13*4882a593Smuzhiyun #define PIN_DAT 0x04 /* Offset of pin data register */ 14*4882a593Smuzhiyun #define PIN_PUD 0x08 /* Offset of pin pull up/down config register */ 15*4882a593Smuzhiyun #define PIN_DRV 0x0C /* Offset of pin drive strength register */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /** 18*4882a593Smuzhiyun * struct samsung_pin_bank_data: represent a controller pin-bank data. 19*4882a593Smuzhiyun * @offset: starting offset of the pin-bank registers. 20*4882a593Smuzhiyun * @nr_pins: number of pins included in this bank. 21*4882a593Smuzhiyun * @name: name to be prefixed for each pin in this pin bank. 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun struct samsung_pin_bank_data { 24*4882a593Smuzhiyun u32 offset; 25*4882a593Smuzhiyun u8 nr_pins; 26*4882a593Smuzhiyun const char *name; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define EXYNOS_PIN_BANK(pins, reg, id) \ 30*4882a593Smuzhiyun { \ 31*4882a593Smuzhiyun .offset = reg, \ 32*4882a593Smuzhiyun .nr_pins = pins, \ 33*4882a593Smuzhiyun .name = id \ 34*4882a593Smuzhiyun } 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /** 37*4882a593Smuzhiyun * struct samsung_pin_ctrl: represent a pin controller. 38*4882a593Smuzhiyun * @pin_banks: list of pin banks included in this controller. 39*4882a593Smuzhiyun * @nr_banks: number of pin banks. 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun struct samsung_pin_ctrl { 42*4882a593Smuzhiyun const struct samsung_pin_bank_data *pin_banks; 43*4882a593Smuzhiyun u32 nr_banks; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /** 47*4882a593Smuzhiyun * struct exynos_pinctrl_priv: exynos pin controller driver private data 48*4882a593Smuzhiyun * @pin_ctrl: pin controller bank information. 49*4882a593Smuzhiyun * @base: base address of the pin controller instance. 50*4882a593Smuzhiyun * @num_banks: number of pin banks included in the pin controller. 51*4882a593Smuzhiyun */ 52*4882a593Smuzhiyun struct exynos_pinctrl_priv { 53*4882a593Smuzhiyun const struct samsung_pin_ctrl *pin_ctrl; 54*4882a593Smuzhiyun unsigned long base; 55*4882a593Smuzhiyun int num_banks; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /** 59*4882a593Smuzhiyun * struct exynos_pinctrl_config_data: configuration for a peripheral. 60*4882a593Smuzhiyun * @offset: offset of the config registers in the controller. 61*4882a593Smuzhiyun * @mask: value of the register to be masked with. 62*4882a593Smuzhiyun * @value: new value to be programmed. 63*4882a593Smuzhiyun */ 64*4882a593Smuzhiyun struct exynos_pinctrl_config_data { 65*4882a593Smuzhiyun const unsigned int offset; 66*4882a593Smuzhiyun const unsigned int mask; 67*4882a593Smuzhiyun const unsigned int value; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun void exynos_pinctrl_setup_peri(struct exynos_pinctrl_config_data *conf, 72*4882a593Smuzhiyun unsigned int num_conf, unsigned long base); 73*4882a593Smuzhiyun int exynos_pinctrl_set_state(struct udevice *dev, 74*4882a593Smuzhiyun struct udevice *config); 75*4882a593Smuzhiyun int exynos_pinctrl_probe(struct udevice *dev); 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #endif /* __PINCTRL_EXYNOS_H_ */ 78