1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <dm.h>
9*4882a593Smuzhiyun #include <errno.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include <dm/pinctrl.h>
12*4882a593Smuzhiyun #include <mach/ar71xx_regs.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun enum periph_id {
17*4882a593Smuzhiyun PERIPH_ID_UART0,
18*4882a593Smuzhiyun PERIPH_ID_SPI0,
19*4882a593Smuzhiyun PERIPH_ID_NONE = -1,
20*4882a593Smuzhiyun };
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun struct ar933x_pinctrl_priv {
23*4882a593Smuzhiyun void __iomem *regs;
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun
pinctrl_ar933x_spi_config(struct ar933x_pinctrl_priv * priv,int cs)26*4882a593Smuzhiyun static void pinctrl_ar933x_spi_config(struct ar933x_pinctrl_priv *priv, int cs)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun switch (cs) {
29*4882a593Smuzhiyun case 0:
30*4882a593Smuzhiyun clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
31*4882a593Smuzhiyun AR933X_GPIO(4), AR933X_GPIO(3) |
32*4882a593Smuzhiyun AR933X_GPIO(5) | AR933X_GPIO(2));
33*4882a593Smuzhiyun setbits_be32(priv->regs + AR71XX_GPIO_REG_FUNC,
34*4882a593Smuzhiyun AR933X_GPIO_FUNC_SPI_EN |
35*4882a593Smuzhiyun AR933X_GPIO_FUNC_RES_TRUE);
36*4882a593Smuzhiyun break;
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
pinctrl_ar933x_uart_config(struct ar933x_pinctrl_priv * priv,int uart_id)40*4882a593Smuzhiyun static void pinctrl_ar933x_uart_config(struct ar933x_pinctrl_priv *priv, int uart_id)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun switch (uart_id) {
43*4882a593Smuzhiyun case PERIPH_ID_UART0:
44*4882a593Smuzhiyun clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
45*4882a593Smuzhiyun AR933X_GPIO(9), AR933X_GPIO(10));
46*4882a593Smuzhiyun setbits_be32(priv->regs + AR71XX_GPIO_REG_FUNC,
47*4882a593Smuzhiyun AR933X_GPIO_FUNC_UART_EN |
48*4882a593Smuzhiyun AR933X_GPIO_FUNC_RES_TRUE);
49*4882a593Smuzhiyun break;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
ar933x_pinctrl_request(struct udevice * dev,int func,int flags)53*4882a593Smuzhiyun static int ar933x_pinctrl_request(struct udevice *dev, int func, int flags)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun struct ar933x_pinctrl_priv *priv = dev_get_priv(dev);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun debug("%s: func=%x, flags=%x\n", __func__, func, flags);
58*4882a593Smuzhiyun switch (func) {
59*4882a593Smuzhiyun case PERIPH_ID_SPI0:
60*4882a593Smuzhiyun pinctrl_ar933x_spi_config(priv, flags);
61*4882a593Smuzhiyun break;
62*4882a593Smuzhiyun case PERIPH_ID_UART0:
63*4882a593Smuzhiyun pinctrl_ar933x_uart_config(priv, func);
64*4882a593Smuzhiyun break;
65*4882a593Smuzhiyun default:
66*4882a593Smuzhiyun return -EINVAL;
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun return 0;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
ar933x_pinctrl_get_periph_id(struct udevice * dev,struct udevice * periph)72*4882a593Smuzhiyun static int ar933x_pinctrl_get_periph_id(struct udevice *dev,
73*4882a593Smuzhiyun struct udevice *periph)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun u32 cell[2];
76*4882a593Smuzhiyun int ret;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
79*4882a593Smuzhiyun "interrupts", cell, ARRAY_SIZE(cell));
80*4882a593Smuzhiyun if (ret < 0)
81*4882a593Smuzhiyun return -EINVAL;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun switch (cell[0]) {
84*4882a593Smuzhiyun case 128:
85*4882a593Smuzhiyun return PERIPH_ID_UART0;
86*4882a593Smuzhiyun case 129:
87*4882a593Smuzhiyun return PERIPH_ID_SPI0;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun return -ENOENT;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
ar933x_pinctrl_set_state_simple(struct udevice * dev,struct udevice * periph)92*4882a593Smuzhiyun static int ar933x_pinctrl_set_state_simple(struct udevice *dev,
93*4882a593Smuzhiyun struct udevice *periph)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun int func;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun func = ar933x_pinctrl_get_periph_id(dev, periph);
98*4882a593Smuzhiyun if (func < 0)
99*4882a593Smuzhiyun return func;
100*4882a593Smuzhiyun return ar933x_pinctrl_request(dev, func, 0);
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun static struct pinctrl_ops ar933x_pinctrl_ops = {
104*4882a593Smuzhiyun .set_state_simple = ar933x_pinctrl_set_state_simple,
105*4882a593Smuzhiyun .request = ar933x_pinctrl_request,
106*4882a593Smuzhiyun .get_periph_id = ar933x_pinctrl_get_periph_id,
107*4882a593Smuzhiyun };
108*4882a593Smuzhiyun
ar933x_pinctrl_probe(struct udevice * dev)109*4882a593Smuzhiyun static int ar933x_pinctrl_probe(struct udevice *dev)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun struct ar933x_pinctrl_priv *priv = dev_get_priv(dev);
112*4882a593Smuzhiyun fdt_addr_t addr;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun addr = devfdt_get_addr(dev);
115*4882a593Smuzhiyun if (addr == FDT_ADDR_T_NONE)
116*4882a593Smuzhiyun return -EINVAL;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun priv->regs = map_physmem(addr,
119*4882a593Smuzhiyun AR71XX_GPIO_SIZE,
120*4882a593Smuzhiyun MAP_NOCACHE);
121*4882a593Smuzhiyun return 0;
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun static const struct udevice_id ar933x_pinctrl_ids[] = {
125*4882a593Smuzhiyun { .compatible = "qca,ar933x-pinctrl" },
126*4882a593Smuzhiyun { }
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun U_BOOT_DRIVER(pinctrl_ar933x) = {
130*4882a593Smuzhiyun .name = "pinctrl_ar933x",
131*4882a593Smuzhiyun .id = UCLASS_PINCTRL,
132*4882a593Smuzhiyun .of_match = ar933x_pinctrl_ids,
133*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct ar933x_pinctrl_priv),
134*4882a593Smuzhiyun .ops = &ar933x_pinctrl_ops,
135*4882a593Smuzhiyun .probe = ar933x_pinctrl_probe,
136*4882a593Smuzhiyun };
137