xref: /OK3568_Linux_fs/u-boot/drivers/pinctrl/Kconfig (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun#
2*4882a593Smuzhiyun# PINCTRL infrastructure and drivers
3*4882a593Smuzhiyun#
4*4882a593Smuzhiyun
5*4882a593Smuzhiyunmenu "Pin controllers"
6*4882a593Smuzhiyun
7*4882a593Smuzhiyunconfig PINCTRL
8*4882a593Smuzhiyun	bool "Support pin controllers"
9*4882a593Smuzhiyun	depends on DM
10*4882a593Smuzhiyun	help
11*4882a593Smuzhiyun	  This enables the basic support for pinctrl framework.  You may want
12*4882a593Smuzhiyun	  to enable some more options depending on what you want to do.
13*4882a593Smuzhiyun
14*4882a593Smuzhiyunconfig PINCTRL_FULL
15*4882a593Smuzhiyun	bool "Support full pin controllers"
16*4882a593Smuzhiyun	depends on PINCTRL && OF_CONTROL
17*4882a593Smuzhiyun	default y
18*4882a593Smuzhiyun	help
19*4882a593Smuzhiyun	  This provides Linux-compatible device tree interface for the pinctrl
20*4882a593Smuzhiyun	  subsystem.  This feature depends on device tree configuration because
21*4882a593Smuzhiyun	  it parses a device tree to look for the pinctrl device which the
22*4882a593Smuzhiyun	  peripheral device is associated with.
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun	  If this option is disabled (it is the only possible choice for non-DT
25*4882a593Smuzhiyun	  boards), the pinctrl core provides no systematic mechanism for
26*4882a593Smuzhiyun	  identifying peripheral devices, applying needed pinctrl settings.
27*4882a593Smuzhiyun	  It is totally up to the implementation of each low-level driver.
28*4882a593Smuzhiyun	  You can save memory footprint in return for some limitations.
29*4882a593Smuzhiyun
30*4882a593Smuzhiyunconfig PINCTRL_GENERIC
31*4882a593Smuzhiyun	bool "Support generic pin controllers"
32*4882a593Smuzhiyun	depends on PINCTRL_FULL
33*4882a593Smuzhiyun	default y
34*4882a593Smuzhiyun	help
35*4882a593Smuzhiyun	  Say Y here if you want to use the pinctrl subsystem through the
36*4882a593Smuzhiyun	  generic DT interface.  If enabled, some functions become available
37*4882a593Smuzhiyun	  to parse common properties such as "pins", "groups", "functions" and
38*4882a593Smuzhiyun	  some pin configuration parameters.  It would be easier if you only
39*4882a593Smuzhiyun	  need the generic DT interface for pin muxing and pin configuration.
40*4882a593Smuzhiyun	  If you need to handle vendor-specific DT properties, you can disable
41*4882a593Smuzhiyun	  this option and implement your own set_state callback in the pinctrl
42*4882a593Smuzhiyun	  operations.
43*4882a593Smuzhiyun
44*4882a593Smuzhiyunconfig PINMUX
45*4882a593Smuzhiyun	bool "Support pin multiplexing controllers"
46*4882a593Smuzhiyun	depends on PINCTRL_GENERIC
47*4882a593Smuzhiyun	default y
48*4882a593Smuzhiyun	help
49*4882a593Smuzhiyun	  This option enables pin multiplexing through the generic pinctrl
50*4882a593Smuzhiyun	  framework. Most SoCs have their own own multiplexing arrangement
51*4882a593Smuzhiyun	  where a single pin can be used for several functions. An SoC pinctrl
52*4882a593Smuzhiyun	  driver allows the required function to be selected for each pin.
53*4882a593Smuzhiyun	  The driver is typically controlled by the device tree.
54*4882a593Smuzhiyun
55*4882a593Smuzhiyunconfig PINCONF
56*4882a593Smuzhiyun	bool "Support pin configuration controllers"
57*4882a593Smuzhiyun	depends on PINCTRL_GENERIC
58*4882a593Smuzhiyun	help
59*4882a593Smuzhiyun	  This option enables pin configuration through the generic pinctrl
60*4882a593Smuzhiyun	  framework.
61*4882a593Smuzhiyun
62*4882a593Smuzhiyunconfig SPL_PINCTRL
63*4882a593Smuzhiyun	bool "Support pin controllers in SPL"
64*4882a593Smuzhiyun	depends on SPL && SPL_DM
65*4882a593Smuzhiyun	help
66*4882a593Smuzhiyun	  This option is an SPL-variant of the PINCTRL option.
67*4882a593Smuzhiyun	  See the help of PINCTRL for details.
68*4882a593Smuzhiyun
69*4882a593Smuzhiyunconfig SPL_PINCTRL_FULL
70*4882a593Smuzhiyun	bool "Support full pin controllers in SPL"
71*4882a593Smuzhiyun	depends on SPL_PINCTRL && SPL_OF_CONTROL
72*4882a593Smuzhiyun	default n if TARGET_STM32F746_DISCO
73*4882a593Smuzhiyun	default y
74*4882a593Smuzhiyun	help
75*4882a593Smuzhiyun	  This option is an SPL-variant of the PINCTRL_FULL option.
76*4882a593Smuzhiyun	  See the help of PINCTRL_FULL for details.
77*4882a593Smuzhiyun
78*4882a593Smuzhiyunconfig SPL_PINCTRL_GENERIC
79*4882a593Smuzhiyun	bool "Support generic pin controllers in SPL"
80*4882a593Smuzhiyun	depends on SPL_PINCTRL_FULL
81*4882a593Smuzhiyun	default y
82*4882a593Smuzhiyun	help
83*4882a593Smuzhiyun	  This option is an SPL-variant of the PINCTRL_GENERIC option.
84*4882a593Smuzhiyun	  See the help of PINCTRL_GENERIC for details.
85*4882a593Smuzhiyun
86*4882a593Smuzhiyunconfig SPL_PINMUX
87*4882a593Smuzhiyun	bool "Support pin multiplexing controllers in SPL"
88*4882a593Smuzhiyun	depends on SPL_PINCTRL_GENERIC
89*4882a593Smuzhiyun	default y
90*4882a593Smuzhiyun	help
91*4882a593Smuzhiyun	  This option is an SPL-variant of the PINMUX option.
92*4882a593Smuzhiyun	  See the help of PINMUX for details.
93*4882a593Smuzhiyun	  The pinctrl subsystem can add a substantial overhead to the SPL
94*4882a593Smuzhiyun	  image since it typically requires quite a few tables either in the
95*4882a593Smuzhiyun	  driver or in the device tree. If this is acceptable and you need
96*4882a593Smuzhiyun	  to adjust pin multiplexing in SPL in order to boot into U-Boot,
97*4882a593Smuzhiyun	  enable this option. You will need to enable device tree in SPL
98*4882a593Smuzhiyun	  for this to work.
99*4882a593Smuzhiyun
100*4882a593Smuzhiyunconfig SPL_PINCONF
101*4882a593Smuzhiyun	bool "Support pin configuration controllers in SPL"
102*4882a593Smuzhiyun	depends on SPL_PINCTRL_GENERIC
103*4882a593Smuzhiyun	help
104*4882a593Smuzhiyun	  This option is an SPL-variant of the PINCONF option.
105*4882a593Smuzhiyun	  See the help of PINCONF for details.
106*4882a593Smuzhiyun
107*4882a593Smuzhiyunif PINCTRL || SPL_PINCTRL
108*4882a593Smuzhiyun
109*4882a593Smuzhiyunconfig PINCTRL_AR933X
110*4882a593Smuzhiyun	bool "QCA/Athores ar933x pin control driver"
111*4882a593Smuzhiyun	depends on DM && SOC_AR933X
112*4882a593Smuzhiyun	help
113*4882a593Smuzhiyun	  Support pin multiplexing control on QCA/Athores ar933x SoCs.
114*4882a593Smuzhiyun	  The driver is controlled by a device tree node which contains
115*4882a593Smuzhiyun	  both the GPIO definitions and pin control functions for each
116*4882a593Smuzhiyun	  available multiplex function.
117*4882a593Smuzhiyun
118*4882a593Smuzhiyunconfig PINCTRL_AT91
119*4882a593Smuzhiyun	bool "AT91 pinctrl driver"
120*4882a593Smuzhiyun	depends on DM
121*4882a593Smuzhiyun	help
122*4882a593Smuzhiyun	  This option is to enable the AT91 pinctrl driver for AT91 PIO
123*4882a593Smuzhiyun	  controller.
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun	  AT91 PIO controller is a combined gpio-controller, pin-mux and
126*4882a593Smuzhiyun	  pin-config module. Each I/O pin may be dedicated as a general-purpose
127*4882a593Smuzhiyun	  I/O or be assigned to a function of an embedded peripheral. Each I/O
128*4882a593Smuzhiyun	  pin has a glitch filter providing rejection of glitches lower than
129*4882a593Smuzhiyun	  one-half of peripheral clock cycle and a debouncing filter providing
130*4882a593Smuzhiyun	  rejection of unwanted pulses from key or push button operations. You
131*4882a593Smuzhiyun	  can also control the multi-driver capability, pull-up and pull-down
132*4882a593Smuzhiyun	  feature on each I/O pin.
133*4882a593Smuzhiyun
134*4882a593Smuzhiyunconfig PINCTRL_AT91PIO4
135*4882a593Smuzhiyun	bool "AT91 PIO4 pinctrl driver"
136*4882a593Smuzhiyun	depends on DM
137*4882a593Smuzhiyun	help
138*4882a593Smuzhiyun	  This option is to enable the AT91 pinctrl driver for AT91 PIO4
139*4882a593Smuzhiyun	  controller which is available on SAMA5D2 SoC.
140*4882a593Smuzhiyun
141*4882a593Smuzhiyunconfig PINCTRL_MAX96745
142*4882a593Smuzhiyun	bool "Maxim MAX96745 pinctrl driver"
143*4882a593Smuzhiyun	depends on DM && I2C_MUX_MAX96745
144*4882a593Smuzhiyun	help
145*4882a593Smuzhiyun	  This option is to enable the pinctrl driver for Maxim
146*4882a593Smuzhiyun	  MAX96745.
147*4882a593Smuzhiyun
148*4882a593Smuzhiyunconfig PINCTRL_MAX96755F
149*4882a593Smuzhiyun	bool "Maxim MAX96755F pinctrl driver"
150*4882a593Smuzhiyun	depends on DM && I2C_MUX_MAX96755F
151*4882a593Smuzhiyun	help
152*4882a593Smuzhiyun	  This option is to enable the pinctrl driver for Maxim
153*4882a593Smuzhiyun	  MAX96755F.
154*4882a593Smuzhiyun
155*4882a593Smuzhiyunconfig PINCTRL_PIC32
156*4882a593Smuzhiyun	bool "Microchip PIC32 pin-control and pin-mux driver"
157*4882a593Smuzhiyun	depends on DM && MACH_PIC32
158*4882a593Smuzhiyun	default y
159*4882a593Smuzhiyun	help
160*4882a593Smuzhiyun	  Supports individual pin selection and configuration for each
161*4882a593Smuzhiyun	  remappable peripheral available on Microchip PIC32
162*4882a593Smuzhiyun	  SoCs. This driver is controlled by a device tree node which
163*4882a593Smuzhiyun	  contains both GPIO defintion and pin control functions.
164*4882a593Smuzhiyun
165*4882a593Smuzhiyunconfig PINCTRL_QCA953X
166*4882a593Smuzhiyun	bool "QCA/Athores qca953x pin control driver"
167*4882a593Smuzhiyun	depends on DM && SOC_QCA953X
168*4882a593Smuzhiyun	help
169*4882a593Smuzhiyun	  Support pin multiplexing control on QCA/Athores qca953x SoCs.
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun	  The driver is controlled by a device tree node which contains both
172*4882a593Smuzhiyun	  the GPIO definitions and pin control functions for each available
173*4882a593Smuzhiyun	  multiplex function.
174*4882a593Smuzhiyun
175*4882a593Smuzhiyunconfig PINCTRL_ROCKCHIP
176*4882a593Smuzhiyun	bool "Rockchip pin control driver"
177*4882a593Smuzhiyun	depends on PINCTRL_FULL && ARCH_ROCKCHIP
178*4882a593Smuzhiyun	default y
179*4882a593Smuzhiyun	help
180*4882a593Smuzhiyun	  Support pin multiplexing control on Rockchip SoCs.
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun	  The driver is controlled by a device tree node which contains both
183*4882a593Smuzhiyun	  the GPIO definitions and pin control functions for each available
184*4882a593Smuzhiyun	  multiplex function.
185*4882a593Smuzhiyun
186*4882a593Smuzhiyunconfig SPL_PINCTRL_ROCKCHIP
187*4882a593Smuzhiyun	bool "Support Rockchip pin controllers in SPL"
188*4882a593Smuzhiyun	depends on SPL_PINCTRL_FULL && ARCH_ROCKCHIP
189*4882a593Smuzhiyun	default y
190*4882a593Smuzhiyun	help
191*4882a593Smuzhiyun	  This option is an SPL-variant of the PINCTRL_ROCKCHIP option.
192*4882a593Smuzhiyun	  See the help of PINCTRL_ROCKCHIP for details.
193*4882a593Smuzhiyun
194*4882a593Smuzhiyunconfig PINCTRL_SANDBOX
195*4882a593Smuzhiyun	bool "Sandbox pinctrl driver"
196*4882a593Smuzhiyun	depends on SANDBOX
197*4882a593Smuzhiyun	help
198*4882a593Smuzhiyun	  This enables pinctrl driver for sandbox.
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun	  Currently, this driver actually does nothing but print debug
201*4882a593Smuzhiyun	  messages when pinctrl operations are invoked.
202*4882a593Smuzhiyun
203*4882a593Smuzhiyunconfig PINCTRL_SINGLE
204*4882a593Smuzhiyun	bool "Single register pin-control and pin-multiplex driver"
205*4882a593Smuzhiyun	depends on DM
206*4882a593Smuzhiyun	help
207*4882a593Smuzhiyun	  This enables pinctrl driver for systems using a single register for
208*4882a593Smuzhiyun	  pin configuration and multiplexing. TI's AM335X SoCs are examples of
209*4882a593Smuzhiyun	  such systems.
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun	  Depending on the platform make sure to also enable OF_TRANSLATE and
212*4882a593Smuzhiyun	  eventually SPL_OF_TRANSLATE to get correct address translations.
213*4882a593Smuzhiyun
214*4882a593Smuzhiyunconfig PINCTRL_STI
215*4882a593Smuzhiyun	bool "STMicroelectronics STi pin-control and pin-mux driver"
216*4882a593Smuzhiyun	depends on DM && ARCH_STI
217*4882a593Smuzhiyun	default y
218*4882a593Smuzhiyun	help
219*4882a593Smuzhiyun	  Support pin multiplexing control on STMicrolectronics STi SoCs.
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun	  The driver is controlled by a device tree node which contains both
222*4882a593Smuzhiyun	  the GPIO definitions and pin control functions for each available
223*4882a593Smuzhiyun	  multiplex function.
224*4882a593Smuzhiyun
225*4882a593Smuzhiyunconfig PINCTRL_STM32
226*4882a593Smuzhiyun	bool "ST STM32 pin control driver"
227*4882a593Smuzhiyun	depends on DM
228*4882a593Smuzhiyun	help
229*4882a593Smuzhiyun	  Supports pin multiplexing control on stm32 SoCs.
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun	  The driver is controlled by a device tree node which contains both
232*4882a593Smuzhiyun	  the GPIO definitions and pin control functions for each available
233*4882a593Smuzhiyun	  multiplex function.
234*4882a593Smuzhiyun
235*4882a593Smuzhiyunconfig ASPEED_AST2500_PINCTRL
236*4882a593Smuzhiyun  bool "Aspeed AST2500 pin control driver"
237*4882a593Smuzhiyun  depends on DM && PINCTRL_GENERIC && ASPEED_AST2500
238*4882a593Smuzhiyun  default y
239*4882a593Smuzhiyun  help
240*4882a593Smuzhiyun    Support pin multiplexing control on Aspeed ast2500 SoC. The driver uses
241*4882a593Smuzhiyun	Generic Pinctrl framework and is compatible with the Linux driver,
242*4882a593Smuzhiyun	i.e. it uses the same device tree configuration.
243*4882a593Smuzhiyun
244*4882a593Smuzhiyunendif
245*4882a593Smuzhiyun
246*4882a593Smuzhiyunsource "drivers/pinctrl/meson/Kconfig"
247*4882a593Smuzhiyunsource "drivers/pinctrl/nxp/Kconfig"
248*4882a593Smuzhiyunsource "drivers/pinctrl/uniphier/Kconfig"
249*4882a593Smuzhiyunsource "drivers/pinctrl/exynos/Kconfig"
250*4882a593Smuzhiyunsource "drivers/pinctrl/mvebu/Kconfig"
251*4882a593Smuzhiyun
252*4882a593Smuzhiyunendmenu
253