1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Rockchip PCIE3.0 phy driver
4 *
5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
6 */
7
8 #include <common.h>
9 #include <clk.h>
10 #include <dm.h>
11 #include <dm/lists.h>
12 #include <generic-phy.h>
13 #include <syscon.h>
14 #include <asm/io.h>
15 #include <asm/arch/clock.h>
16 #include <regmap.h>
17 #include <reset-uclass.h>
18
19 /* Register for RK3568 */
20 #define GRF_PCIE30PHY_RK3568_CON1 0x4
21 #define GRF_PCIE30PHY_RK3568_CON4 0x10
22 #define GRF_PCIE30PHY_RK3568_CON6 0x18
23 #define GRF_PCIE30PHY_RK3568_CON9 0x24
24 #define GRF_PCIE30PHY_RK3568_STATUS0 0x80
25 #define RK3568_SRAM_INIT_DONE(reg) (reg & BIT(14))
26
27 /* Register for RK3588 */
28 #define PHP_GRF_PCIESEL_CON 0x100
29 #define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0
30 #define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904
31 #define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04
32
33 /*
34 * pcie30_phy_mode[2:0]
35 * bit2: aggregation
36 * bit1: bifurcation for port 1
37 * bit0: bifurcation for port 0
38 */
39 #define PHY_MODE_PCIE_AGGREGATION 4 /* PCIe3x4 */
40 #define PHY_MODE_PCIE_NANBNB 0 /* P1:PCIe3x2 + P0:PCIe3x2 */
41 #define PHY_MODE_PCIE_NANBBI 1 /* P1:PCIe3x2 + P0:PCIe3x1*2 */
42 #define PHY_MODE_PCIE_NABINB 2 /* P1:PCIe3x1*2 + P0:PCIe3x2 */
43 #define PHY_MODE_PCIE_NABIBI 3 /* P1:PCIe3x1*2 + P0:PCIe3x1*2 */
44
45 struct rockchip_p3phy_ops;
46
47 struct rockchip_p3phy_priv {
48 const struct rockchip_p3phy_ops *ops;
49 struct clk_bulk clks;
50 void __iomem *mmio;
51 int mode;
52 struct regmap *phy_grf;
53 struct regmap *pipe_grf;
54 struct reset_ctl p30phy;
55 bool is_bifurcation;
56 /* pcie30_phymode: Aggregation, Bifurcation */
57 int pcie30_phymode;
58 };
59
60 struct rockchip_p3phy_ops {
61 int (*phy_init)(struct rockchip_p3phy_priv *priv);
62 };
63
64 static const u16 phy_fw[] = {
65 #include "phy-rockchip-snps-pcie3.fw"
66 };
67
rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv * priv)68 static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv)
69 {
70 int i, ret = 0;
71 u32 reg;
72
73 /* Deassert PCIe PMA output clamp mode */
74 regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON9,
75 (0x1 << 15) | (0x1 << 31));
76
77 /* Set bifurcation if needed */
78 if (priv->is_bifurcation) {
79 regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON6,
80 0x1 | (0xf << 16));
81 regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON1,
82 (0x1 << 15) | (0x1 << 31));
83 }
84
85 regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON4,
86 (0x0 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
87 regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON4,
88 (0x0 << 13) | (0x1 << (13 + 16))); //sdram_bypass
89 reset_deassert(&priv->p30phy);
90 udelay(5);
91 ret = regmap_read_poll_timeout(priv->phy_grf,
92 GRF_PCIE30PHY_RK3568_STATUS0,
93 reg, RK3568_SRAM_INIT_DONE(reg),
94 0, 500);
95 if (ret) {
96 pr_err("%s: lock failed 0x%x, check refclk and power\n",
97 __func__, reg);
98 return -ETIMEDOUT;
99 }
100
101 regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON9,
102 (0x3 << 8) | (0x3 << (8 + 16))); //map to access sram
103 for (i = 0; i < ARRAY_SIZE(phy_fw); i++)
104 writel(phy_fw[i], priv->mmio + (i<<2));
105 printf("snps pcie3phy FW update! size %ld\n", ARRAY_SIZE(phy_fw));
106 regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON9,
107 (0x0 << 8) | (0x3 << (8 + 16)));
108 regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON4,
109 (0x1 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
110
111 udelay(10);
112
113 return 0;
114 }
115
116 static const struct rockchip_p3phy_ops rk3568_ops = {
117 .phy_init = &rockchip_p3phy_rk3568_init,
118 };
119
rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv * priv)120 static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv)
121 {
122 u32 reg;
123 u32 timeout;
124
125 /* Deassert PCIe PMA output clamp mode */
126 regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,
127 (0x1 << 8) | (0x1 << 24));
128
129 /* Select correct pcie30_phymode */
130 if (priv->pcie30_phymode > 4)
131 priv->pcie30_phymode = PHY_MODE_PCIE_AGGREGATION;
132
133 regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,
134 (0x7<<16) | priv->pcie30_phymode);
135
136 /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
137 reg = priv->pcie30_phymode & 3;
138 if (reg)
139 regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON,
140 (reg << 16) | reg);
141
142 timeout = 500;
143 while (timeout--) {
144 regmap_read(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_STATUS1, ®);
145 if (reg & 0x1)
146 break;
147 udelay(1);
148 }
149
150 if (timeout <= 0) {
151 pr_err("%s: phy0 lock failed, check input refclk and power supply\n", __func__);
152 return -ETIMEDOUT;
153 }
154
155 timeout = 500;
156 while (timeout--) {
157 regmap_read(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY1_STATUS1, ®);
158 if (reg & 0x1)
159 break;
160 udelay(1);
161 }
162
163 if (timeout <= 0) {
164 pr_err("%s: phy1 lock failed, check input refclk and power supply\n", __func__);
165 return -ETIMEDOUT;
166 }
167
168 reset_deassert(&priv->p30phy);
169 udelay(5);
170
171 return 0;
172 }
173
174 static const struct rockchip_p3phy_ops rk3588_ops = {
175 .phy_init = &rockchip_p3phy_rk3588_init,
176 };
177
rochchip_p3phy_init(struct phy * phy)178 static int rochchip_p3phy_init(struct phy *phy)
179 {
180 struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
181 int ret;
182
183 ret = clk_enable_bulk(&priv->clks);
184 if (ret) {
185 pr_err("failed to enable clks (ret=%d)\n", ret);
186 return ret;
187 }
188
189 reset_assert(&priv->p30phy);
190 udelay(1);
191
192 if (priv->ops->phy_init) {
193 ret = priv->ops->phy_init(priv);
194 if (ret) {
195 clk_disable_bulk(&priv->clks);
196 return ret;
197 }
198
199 }
200
201 return 0;
202 }
203
rochchip_p3phy_exit(struct phy * phy)204 static int rochchip_p3phy_exit(struct phy *phy)
205 {
206 struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
207
208 clk_disable_bulk(&priv->clks);
209 reset_assert(&priv->p30phy);
210 return 0;
211 }
212
rockchip_p3phy_probe(struct udevice * dev)213 static int rockchip_p3phy_probe(struct udevice *dev)
214 {
215 struct rockchip_p3phy_priv *priv = dev_get_priv(dev);
216 dev_get_driver_data(dev);
217 struct udevice *syscon;
218 int ret;
219
220 priv->mmio = (void __iomem *)dev_read_addr(dev);
221 if ((fdt_addr_t)priv->mmio == FDT_ADDR_T_NONE)
222 return -EINVAL;
223
224 priv->ops = (struct rockchip_p3phy_ops *)dev_get_driver_data(dev);
225 if (!priv->ops) {
226 dev_err(dev, "no of match data provided\n");
227 return -EINVAL;
228 }
229
230 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
231 "rockchip,phy-grf", &syscon);
232 if (ret) {
233 pr_err("unable to find syscon device for rockchip,phy-grf\n");
234 return ret;
235 }
236
237 priv->phy_grf = syscon_get_regmap(syscon);
238 if (IS_ERR(priv->phy_grf)) {
239 dev_err(dev, "failed to find rockchip,phy_grf regmap\n");
240 return PTR_ERR(priv->phy_grf);
241 }
242
243 dev_dbg(priv->dev, "phy_grf is 0x%llx\n", priv->phy_grf->base);
244
245 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
246 "rockchip,pipe-grf", &syscon);
247 if (ret) {
248 /* It's optional, rk3568 doesn't need it */
249 priv->pipe_grf = NULL;
250 pr_err("unable to get syscon device for rockchip,pipe-grf\n");
251 goto skip_pipe_grf;
252 }
253
254 priv->pipe_grf = syscon_get_regmap(syscon);
255 if (IS_ERR(priv->pipe_grf))
256 dev_err(dev, "failed to find rockchip,pipe_grf regmap\n");
257
258
259 priv->pcie30_phymode = dev_read_u32_default(dev, "rockchip,pcie30-phymode", PHY_MODE_PCIE_AGGREGATION);
260
261 skip_pipe_grf:
262 ret = reset_get_by_name(dev, "phy", &priv->p30phy);
263 if (ret) {
264 dev_err(dev, "no phy reset control specified\n");
265 return ret;
266 }
267
268 if (ret) {
269 dev_err(dev, "Can't get clock: %d\n", ret);
270 return ret;
271 }
272
273 return 0;
274 }
275
rockchip_p3phy_configure(struct phy * phy,union phy_configure_opts * opts)276 static int rockchip_p3phy_configure(struct phy *phy, union phy_configure_opts *opts)
277 {
278 struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
279
280 priv->is_bifurcation = opts->pcie.is_bifurcation;
281
282 return 0;
283 }
284
285 static struct phy_ops rochchip_p3phy_ops = {
286 .init = rochchip_p3phy_init,
287 .exit = rochchip_p3phy_exit,
288 .configure = rockchip_p3phy_configure,
289 };
290
291 static const struct udevice_id rockchip_p3phy_of_match[] = {
292 { .compatible = "rockchip,rk3568-pcie3-phy", .data = (ulong)&rk3568_ops},
293 { .compatible = "rockchip,rk3588-pcie3-phy", .data = (ulong)&rk3588_ops },
294 { },
295 };
296
297 U_BOOT_DRIVER(rockchip_pcie3phy) = {
298 .name = "rockchip_pcie3phy",
299 .id = UCLASS_PHY,
300 .of_match = rockchip_p3phy_of_match,
301 .ops = &rochchip_p3phy_ops,
302 .probe = rockchip_p3phy_probe,
303 .priv_auto_alloc_size = sizeof(struct rockchip_p3phy_priv),
304 };
305