1 /*
2 * Copyright 2017 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <dm/lists.h>
10 #include <generic-phy.h>
11 #include <linux/ioport.h>
12 #include <power/regulator.h>
13 #include <regmap.h>
14 #include <syscon.h>
15 #include <asm/io.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/cpu.h>
18 #include <reset-uclass.h>
19
20 #include "../usb/gadget/dwc2_udc_otg_priv.h"
21
22 #define U2PHY_BIT_WRITEABLE_SHIFT 16
23 #define CHG_DCD_MAX_RETRIES 6
24 #define CHG_PRI_MAX_RETRIES 2
25 #define CHG_DCD_POLL_TIME 100 /* millisecond */
26 #define CHG_PRIMARY_DET_TIME 40 /* millisecond */
27 #define CHG_SECONDARY_DET_TIME 40 /* millisecond */
28
29 struct rockchip_usb2phy;
30
31 enum power_supply_type {
32 POWER_SUPPLY_TYPE_UNKNOWN = 0,
33 POWER_SUPPLY_TYPE_USB, /* Standard Downstream Port */
34 POWER_SUPPLY_TYPE_USB_DCP, /* Dedicated Charging Port */
35 POWER_SUPPLY_TYPE_USB_CDP, /* Charging Downstream Port */
36 POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */
37 };
38
39 enum rockchip_usb2phy_port_id {
40 USB2PHY_PORT_OTG,
41 USB2PHY_PORT_HOST,
42 USB2PHY_NUM_PORTS,
43 };
44
45 struct usb2phy_reg {
46 u32 offset;
47 u32 bitend;
48 u32 bitstart;
49 u32 disable;
50 u32 enable;
51 };
52
53 /**
54 * struct rockchip_chg_det_reg: usb charger detect registers
55 * @cp_det: charging port detected successfully.
56 * @dcp_det: dedicated charging port detected successfully.
57 * @dp_det: assert data pin connect successfully.
58 * @idm_sink_en: open dm sink curren.
59 * @idp_sink_en: open dp sink current.
60 * @idp_src_en: open dm source current.
61 * @rdm_pdwn_en: open dm pull down resistor.
62 * @vdm_src_en: open dm voltage source.
63 * @vdp_src_en: open dp voltage source.
64 * @opmode: utmi operational mode.
65 */
66 struct rockchip_chg_det_reg {
67 struct usb2phy_reg cp_det;
68 struct usb2phy_reg dcp_det;
69 struct usb2phy_reg dp_det;
70 struct usb2phy_reg idm_sink_en;
71 struct usb2phy_reg idp_sink_en;
72 struct usb2phy_reg idp_src_en;
73 struct usb2phy_reg rdm_pdwn_en;
74 struct usb2phy_reg vdm_src_en;
75 struct usb2phy_reg vdp_src_en;
76 struct usb2phy_reg opmode;
77 };
78
79 /**
80 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration.
81 * @phy_sus: phy suspend register.
82 * @bvalid_det_en: vbus valid rise detection enable register.
83 * @bvalid_det_st: vbus valid rise detection status register.
84 * @bvalid_det_clr: vbus valid rise detection clear register.
85 * @ls_det_en: linestate detection enable register.
86 * @ls_det_st: linestate detection state register.
87 * @ls_det_clr: linestate detection clear register.
88 * @iddig_output: iddig output from grf.
89 * @iddig_en: utmi iddig select between grf and phy,
90 * 0: from phy; 1: from grf
91 * @idfall_det_en: id fall detection enable register.
92 * @idfall_det_st: id fall detection state register.
93 * @idfall_det_clr: id fall detection clear register.
94 * @idrise_det_en: id rise detection enable register.
95 * @idrise_det_st: id rise detection state register.
96 * @idrise_det_clr: id rise detection clear register.
97 * @utmi_avalid: utmi vbus avalid status register.
98 * @utmi_bvalid: utmi vbus bvalid status register.
99 * @utmi_iddig: otg port id pin status register.
100 * @utmi_ls: utmi linestate state register.
101 * @utmi_hstdet: utmi host disconnect register.
102 * @vbus_det_en: vbus detect function power down register.
103 */
104 struct rockchip_usb2phy_port_cfg {
105 struct usb2phy_reg phy_sus;
106 struct usb2phy_reg bvalid_det_en;
107 struct usb2phy_reg bvalid_det_st;
108 struct usb2phy_reg bvalid_det_clr;
109 struct usb2phy_reg ls_det_en;
110 struct usb2phy_reg ls_det_st;
111 struct usb2phy_reg ls_det_clr;
112 struct usb2phy_reg iddig_output;
113 struct usb2phy_reg iddig_en;
114 struct usb2phy_reg idfall_det_en;
115 struct usb2phy_reg idfall_det_st;
116 struct usb2phy_reg idfall_det_clr;
117 struct usb2phy_reg idrise_det_en;
118 struct usb2phy_reg idrise_det_st;
119 struct usb2phy_reg idrise_det_clr;
120 struct usb2phy_reg utmi_avalid;
121 struct usb2phy_reg utmi_bvalid;
122 struct usb2phy_reg utmi_iddig;
123 struct usb2phy_reg utmi_ls;
124 struct usb2phy_reg utmi_hstdet;
125 struct usb2phy_reg vbus_det_en;
126 };
127
128 /**
129 * struct rockchip_usb2phy_cfg: usb-phy configuration.
130 * @reg: the address offset of grf for usb-phy config.
131 * @num_ports: specify how many ports that the phy has.
132 * @phy_tuning: phy default parameters tunning.
133 * @clkout_ctl: keep on/turn off output clk of phy.
134 * @chg_det: charger detection registers.
135 */
136 struct rockchip_usb2phy_cfg {
137 u32 reg;
138 u32 num_ports;
139 int (*phy_tuning)(struct rockchip_usb2phy *);
140 struct usb2phy_reg clkout_ctl;
141 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
142 const struct rockchip_chg_det_reg chg_det;
143 };
144
145 /**
146 * @dcd_retries: The retry count used to track Data contact
147 * detection process.
148 * @primary_retries: The retry count used to do usb bc detection
149 * primary stage.
150 * @grf: General Register Files register base.
151 * @usbgrf_base : USB General Register Files register base.
152 * @phy_base: the base address of USB PHY.
153 * @phy_rst: phy reset control.
154 * @phy_cfg: phy register configuration, assigned by driver data.
155 */
156 struct rockchip_usb2phy {
157 u8 dcd_retries;
158 u8 primary_retries;
159 struct regmap *grf_base;
160 struct regmap *usbgrf_base;
161 void __iomem *phy_base;
162 struct udevice *vbus_supply[USB2PHY_NUM_PORTS];
163 struct reset_ctl phy_rst;
164 const struct rockchip_usb2phy_cfg *phy_cfg;
165 };
166
get_reg_base(struct rockchip_usb2phy * rphy)167 static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy)
168 {
169 return !rphy->usbgrf_base ? rphy->grf_base : rphy->usbgrf_base;
170 }
171
property_enable(struct regmap * base,const struct usb2phy_reg * reg,bool en)172 static inline int property_enable(struct regmap *base,
173 const struct usb2phy_reg *reg, bool en)
174 {
175 u32 val, mask, tmp;
176
177 tmp = en ? reg->enable : reg->disable;
178 mask = GENMASK(reg->bitend, reg->bitstart);
179 val = (tmp << reg->bitstart) | (mask << U2PHY_BIT_WRITEABLE_SHIFT);
180
181 return regmap_write(base, reg->offset, val);
182 }
183
property_enabled(struct regmap * base,const struct usb2phy_reg * reg)184 static inline bool property_enabled(struct regmap *base,
185 const struct usb2phy_reg *reg)
186 {
187 u32 tmp, orig;
188 u32 mask = GENMASK(reg->bitend, reg->bitstart);
189
190 regmap_read(base, reg->offset, &orig);
191
192 tmp = (orig & mask) >> reg->bitstart;
193
194 return tmp == reg->enable;
195 }
196
chg_to_string(enum power_supply_type chg_type)197 static const char *chg_to_string(enum power_supply_type chg_type)
198 {
199 switch (chg_type) {
200 case POWER_SUPPLY_TYPE_USB:
201 return "USB_SDP_CHARGER";
202 case POWER_SUPPLY_TYPE_USB_DCP:
203 return "USB_DCP_CHARGER";
204 case POWER_SUPPLY_TYPE_USB_CDP:
205 return "USB_CDP_CHARGER";
206 case POWER_SUPPLY_TYPE_USB_FLOATING:
207 return "USB_FLOATING_CHARGER";
208 default:
209 return "INVALID_CHARGER";
210 }
211 }
212
rockchip_chg_enable_dcd(struct rockchip_usb2phy * rphy,bool en)213 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
214 bool en)
215 {
216 struct regmap *base = get_reg_base(rphy);
217
218 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
219 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en);
220 }
221
rockchip_chg_enable_primary_det(struct rockchip_usb2phy * rphy,bool en)222 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
223 bool en)
224 {
225 struct regmap *base = get_reg_base(rphy);
226
227 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en);
228 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en);
229 }
230
rockchip_chg_enable_secondary_det(struct rockchip_usb2phy * rphy,bool en)231 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
232 bool en)
233 {
234 struct regmap *base = get_reg_base(rphy);
235
236 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en);
237 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en);
238 }
239
rockchip_chg_primary_det_retry(struct rockchip_usb2phy * rphy)240 static bool rockchip_chg_primary_det_retry(struct rockchip_usb2phy *rphy)
241 {
242 bool vout = false;
243 struct regmap *base = get_reg_base(rphy);
244
245 while (rphy->primary_retries--) {
246 /* voltage source on DP, probe on DM */
247 rockchip_chg_enable_primary_det(rphy, true);
248 mdelay(CHG_PRIMARY_DET_TIME);
249 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det);
250 if (vout)
251 break;
252 }
253
254 rockchip_chg_enable_primary_det(rphy, false);
255 return vout;
256 }
257
rockchip_chg_get_type(void)258 int rockchip_chg_get_type(void)
259 {
260 const struct rockchip_usb2phy_port_cfg *port_cfg;
261 enum power_supply_type chg_type;
262 struct rockchip_usb2phy *rphy;
263 struct udevice *udev;
264 struct regmap *base;
265 bool is_dcd, vout;
266 int ret;
267
268 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev);
269 if (ret == -ENODEV) {
270 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2phy", &udev);
271 if (ret) {
272 pr_err("%s: get usb2 phy node failed: %d\n", __func__, ret);
273 return ret;
274 }
275 }
276
277 rphy = dev_get_priv(udev);
278 base = get_reg_base(rphy);
279 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
280
281 /* Check USB-Vbus status first */
282 if (!property_enabled(base, &port_cfg->utmi_bvalid)) {
283 pr_info("%s: no charger found\n", __func__);
284 return POWER_SUPPLY_TYPE_UNKNOWN;
285 }
286
287 #ifdef CONFIG_ROCKCHIP_RK3036
288 chg_type = POWER_SUPPLY_TYPE_USB;
289 goto out;
290 #endif
291
292 /* Suspend USB-PHY and put the controller in non-driving mode */
293 property_enable(base, &port_cfg->phy_sus, true);
294 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false);
295
296 rphy->dcd_retries = CHG_DCD_MAX_RETRIES;
297 rphy->primary_retries = CHG_PRI_MAX_RETRIES;
298
299 /* stage 1, start DCD processing stage */
300 rockchip_chg_enable_dcd(rphy, true);
301
302 while (rphy->dcd_retries--) {
303 mdelay(CHG_DCD_POLL_TIME);
304
305 /* get data contact detection status */
306 is_dcd = property_enabled(base, &rphy->phy_cfg->chg_det.dp_det);
307
308 if (is_dcd || !rphy->dcd_retries) {
309 /*
310 * stage 2, turn off DCD circuitry, then
311 * voltage source on DP, probe on DM.
312 */
313 rockchip_chg_enable_dcd(rphy, false);
314 rockchip_chg_enable_primary_det(rphy, true);
315 break;
316 }
317 }
318
319 mdelay(CHG_PRIMARY_DET_TIME);
320 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det);
321 rockchip_chg_enable_primary_det(rphy, false);
322 if (vout) {
323 /* stage 3, voltage source on DM, probe on DP */
324 rockchip_chg_enable_secondary_det(rphy, true);
325 } else {
326 if (!rphy->dcd_retries) {
327 /* floating charger found */
328 chg_type = POWER_SUPPLY_TYPE_USB_FLOATING;
329 goto out;
330 } else {
331 /*
332 * Retry some times to make sure that it's
333 * really a USB SDP charger.
334 */
335 vout = rockchip_chg_primary_det_retry(rphy);
336 if (vout) {
337 /* stage 3, voltage source on DM, probe on DP */
338 rockchip_chg_enable_secondary_det(rphy, true);
339 } else {
340 /* USB SDP charger found */
341 chg_type = POWER_SUPPLY_TYPE_USB;
342 goto out;
343 }
344 }
345 }
346
347 mdelay(CHG_SECONDARY_DET_TIME);
348 vout = property_enabled(base, &rphy->phy_cfg->chg_det.dcp_det);
349 /* stage 4, turn off voltage source */
350 rockchip_chg_enable_secondary_det(rphy, false);
351 if (vout)
352 chg_type = POWER_SUPPLY_TYPE_USB_DCP;
353 else
354 chg_type = POWER_SUPPLY_TYPE_USB_CDP;
355
356 out:
357 /* Resume USB-PHY and put the controller in normal mode */
358 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true);
359 property_enable(base, &port_cfg->phy_sus, false);
360
361 debug("charger is %s\n", chg_to_string(chg_type));
362
363 return chg_type;
364 }
365
rockchip_u2phy_vbus_detect(void)366 int rockchip_u2phy_vbus_detect(void)
367 {
368 int chg_type;
369
370 chg_type = rockchip_chg_get_type();
371
372 return (chg_type == POWER_SUPPLY_TYPE_USB ||
373 chg_type == POWER_SUPPLY_TYPE_USB_CDP) ? 1 : 0;
374 }
375
otg_phy_init(struct dwc2_udc * dev)376 void otg_phy_init(struct dwc2_udc *dev)
377 {
378 const struct rockchip_usb2phy_port_cfg *port_cfg;
379 struct rockchip_usb2phy *rphy;
380 struct udevice *udev;
381 struct regmap *base;
382 int ret;
383
384 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev);
385 if (ret == -ENODEV) {
386 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2phy", &udev);
387 if (ret) {
388 pr_err("%s: get usb2 phy node failed: %d\n", __func__, ret);
389 return;
390 }
391 }
392
393 rphy = dev_get_priv(udev);
394 base = get_reg_base(rphy);
395 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
396
397 /* Set the USB-PHY COMMONONN to 1'b0 to ensure USB's clocks */
398 if(rphy->phy_cfg->clkout_ctl.disable)
399 property_enable(base, &rphy->phy_cfg->clkout_ctl, true);
400
401 /* Reset USB-PHY */
402 property_enable(base, &port_cfg->phy_sus, true);
403 udelay(20);
404 property_enable(base, &port_cfg->phy_sus, false);
405 mdelay(2);
406 }
407
rockchip_usb2phy_reset(struct rockchip_usb2phy * rphy)408 static int rockchip_usb2phy_reset(struct rockchip_usb2phy *rphy)
409 {
410 int ret;
411
412 if (rphy->phy_rst.dev) {
413 ret = reset_assert(&rphy->phy_rst);
414 if (ret < 0) {
415 pr_err("u2phy assert reset failed: %d", ret);
416 return ret;
417 }
418
419 udelay(20);
420
421 ret = reset_deassert(&rphy->phy_rst);
422 if (ret < 0) {
423 pr_err("u2phy deassert reset failed: %d", ret);
424 return ret;
425 }
426
427 udelay(100);
428 }
429
430 return 0;
431 }
432
rockchip_usb2phy_init(struct phy * phy)433 static int rockchip_usb2phy_init(struct phy *phy)
434 {
435 struct udevice *parent = phy->dev->parent;
436 struct rockchip_usb2phy *rphy = dev_get_priv(parent);
437 const struct rockchip_usb2phy_port_cfg *port_cfg;
438 struct regmap *base = get_reg_base(rphy);
439
440 if (phy->id == USB2PHY_PORT_OTG) {
441 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
442 } else if (phy->id == USB2PHY_PORT_HOST) {
443 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
444 } else {
445 dev_err(phy->dev, "phy id %lu not support", phy->id);
446 return -EINVAL;
447 }
448
449 property_enable(base, &port_cfg->phy_sus, false);
450
451 /* waiting for the utmi_clk to become stable */
452 udelay(2000);
453
454 return 0;
455 }
456
rockchip_usb2phy_exit(struct phy * phy)457 static int rockchip_usb2phy_exit(struct phy *phy)
458 {
459 struct udevice *parent = phy->dev->parent;
460 struct rockchip_usb2phy *rphy = dev_get_priv(parent);
461 const struct rockchip_usb2phy_port_cfg *port_cfg;
462 struct regmap *base = get_reg_base(rphy);
463
464 if (phy->id == USB2PHY_PORT_OTG) {
465 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
466 } else if (phy->id == USB2PHY_PORT_HOST) {
467 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
468 } else {
469 dev_err(phy->dev, "phy id %lu not support", phy->id);
470 return -EINVAL;
471 }
472
473 property_enable(base, &port_cfg->phy_sus, true);
474
475 return 0;
476 }
477
rockchip_usb2phy_power_on(struct phy * phy)478 static int rockchip_usb2phy_power_on(struct phy *phy)
479 {
480 struct udevice *parent = phy->dev->parent;
481 struct rockchip_usb2phy *rphy = dev_get_priv(parent);
482 struct udevice *vbus = rphy->vbus_supply[phy->id];
483 int ret;
484
485 if (vbus) {
486 ret = regulator_set_enable(vbus, true);
487 if (ret) {
488 pr_err("%s: Failed to set VBus supply\n", __func__);
489 return ret;
490 }
491 }
492
493 return 0;
494 }
495
rockchip_usb2phy_power_off(struct phy * phy)496 static int rockchip_usb2phy_power_off(struct phy *phy)
497 {
498 struct udevice *parent = phy->dev->parent;
499 struct rockchip_usb2phy *rphy = dev_get_priv(parent);
500 struct udevice *vbus = rphy->vbus_supply[phy->id];
501 int ret;
502
503 if (vbus) {
504 ret = regulator_set_enable(vbus, false);
505 if (ret) {
506 pr_err("%s: Failed to set VBus supply\n", __func__);
507 return ret;
508 }
509 }
510
511 return 0;
512 }
513
rockchip_usb2phy_of_xlate(struct phy * phy,struct ofnode_phandle_args * args)514 static int rockchip_usb2phy_of_xlate(struct phy *phy,
515 struct ofnode_phandle_args *args)
516 {
517 const char *dev_name = phy->dev->name;
518 struct udevice *parent = phy->dev->parent;
519 struct rockchip_usb2phy *rphy = dev_get_priv(parent);
520
521 if (!strcasecmp(dev_name, "host-port")) {
522 phy->id = USB2PHY_PORT_HOST;
523 device_get_supply_regulator(phy->dev, "phy-supply",
524 &rphy->vbus_supply[USB2PHY_PORT_HOST]);
525 } else if (!strcasecmp(dev_name, "otg-port")) {
526 phy->id = USB2PHY_PORT_OTG;
527 device_get_supply_regulator(phy->dev, "phy-supply",
528 &rphy->vbus_supply[USB2PHY_PORT_OTG]);
529 if (!rphy->vbus_supply[USB2PHY_PORT_OTG])
530 device_get_supply_regulator(phy->dev, "vbus-supply",
531 &rphy->vbus_supply[USB2PHY_PORT_OTG]);
532 } else {
533 pr_err("%s: invalid dev name\n", __func__);
534 return -EINVAL;
535 }
536
537 return 0;
538 }
539
rockchip_usb2phy_bind(struct udevice * dev)540 static int rockchip_usb2phy_bind(struct udevice *dev)
541 {
542 struct udevice *child;
543 ofnode subnode;
544 const char *node_name;
545 int ret;
546
547 dev_for_each_subnode(subnode, dev) {
548 if (!ofnode_valid(subnode)) {
549 debug("%s: %s subnode not found", __func__, dev->name);
550 return -ENXIO;
551 }
552
553 node_name = ofnode_get_name(subnode);
554 debug("%s: subnode %s\n", __func__, node_name);
555
556 ret = device_bind_driver_to_node(dev, "rockchip_usb2phy_port",
557 node_name, subnode, &child);
558 if (ret) {
559 pr_err("%s: '%s' cannot bind 'rockchip_usb2phy_port'\n",
560 __func__, node_name);
561 return ret;
562 }
563 }
564
565 return 0;
566 }
567
rockchip_usb2phy_probe(struct udevice * dev)568 static int rockchip_usb2phy_probe(struct udevice *dev)
569 {
570 const struct rockchip_usb2phy_cfg *phy_cfgs;
571 struct rockchip_usb2phy *rphy = dev_get_priv(dev);
572 struct udevice *parent = dev->parent;
573 struct udevice *syscon;
574 struct resource res;
575 u32 reg, index;
576 int ret;
577
578 rphy->phy_base = (void __iomem *)dev_read_addr(dev);
579 if (IS_ERR(rphy->phy_base)) {
580 dev_err(dev, "get the base address of usb phy failed\n");
581 }
582
583 if (!strncmp(parent->name, "root_driver", 11) &&
584 dev_read_bool(dev, "rockchip,grf")) {
585 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
586 "rockchip,grf", &syscon);
587 if (ret) {
588 dev_err(dev, "get syscon grf failed\n");
589 return ret;
590 }
591
592 rphy->grf_base = syscon_get_regmap(syscon);
593 } else {
594 rphy->grf_base = syscon_get_regmap(parent);
595 }
596
597 if (rphy->grf_base <= 0) {
598 dev_err(dev, "get syscon grf regmap failed\n");
599 return -EINVAL;
600 }
601
602 if (dev_read_bool(dev, "rockchip,usbgrf")) {
603 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
604 "rockchip,usbgrf", &syscon);
605 if (ret) {
606 dev_err(dev, "get syscon usbgrf failed\n");
607 return ret;
608 }
609
610 rphy->usbgrf_base = syscon_get_regmap(syscon);
611 if (rphy->usbgrf_base <= 0) {
612 dev_err(dev, "get syscon usbgrf regmap failed\n");
613 return -EINVAL;
614 }
615 } else {
616 rphy->usbgrf_base = NULL;
617 }
618
619 if (!strncmp(parent->name, "root_driver", 11)) {
620 ret = dev_read_resource(dev, 0, &res);
621 reg = res.start;
622 } else {
623 ret = ofnode_read_u32(dev_ofnode(dev), "reg", ®);
624 }
625
626 if (ret) {
627 dev_err(dev, "could not read reg\n");
628 return -EINVAL;
629 }
630
631 ret = reset_get_by_name(dev, "phy", &rphy->phy_rst);
632 if (ret)
633 dev_dbg(dev, "no u2phy reset control specified\n");
634
635 phy_cfgs =
636 (const struct rockchip_usb2phy_cfg *)dev_get_driver_data(dev);
637 if (!phy_cfgs) {
638 dev_err(dev, "unable to get phy_cfgs\n");
639 return -EINVAL;
640 }
641
642 /* find out a proper config which can be matched with dt. */
643 index = 0;
644 do {
645 if (phy_cfgs[index].reg == reg) {
646 rphy->phy_cfg = &phy_cfgs[index];
647 break;
648 }
649 ++index;
650 } while (phy_cfgs[index].reg);
651
652 if (!rphy->phy_cfg) {
653 dev_err(dev, "no phy-config can be matched\n");
654 return -EINVAL;
655 }
656
657 if (rphy->phy_cfg->phy_tuning)
658 rphy->phy_cfg->phy_tuning(rphy);
659
660 return 0;
661 }
662
rk322x_usb2phy_tuning(struct rockchip_usb2phy * rphy)663 static int rk322x_usb2phy_tuning(struct rockchip_usb2phy *rphy)
664 {
665 struct regmap *base = get_reg_base(rphy);
666 int ret = 0;
667
668 /* Open pre-emphasize in non-chirp state for PHY0 otg port */
669 if (rphy->phy_cfg->reg == 0x760)
670 ret = regmap_write(base, 0x76c, 0x00070004);
671
672 return ret;
673 }
674
rk3308_usb2phy_tuning(struct rockchip_usb2phy * rphy)675 static int rk3308_usb2phy_tuning(struct rockchip_usb2phy *rphy)
676 {
677 struct regmap *base = get_reg_base(rphy);
678 unsigned int tmp, orig;
679 int ret;
680
681 if (soc_is_rk3308bs()) {
682 /* Enable otg/host port pre-emphasis during non-chirp phase */
683 ret = regmap_read(base, 0, &orig);
684 if (ret)
685 return ret;
686 tmp = orig & ~GENMASK(2, 0);
687 tmp |= BIT(2) & GENMASK(2, 0);
688 ret = regmap_write(base, 0, tmp);
689 if (ret)
690 return ret;
691
692 /* Set otg port squelch trigger point configure to 100mv */
693 ret = regmap_read(base, 0x004, &orig);
694 if (ret)
695 return ret;
696 tmp = orig & ~GENMASK(7, 5);
697 tmp |= 0x40 & GENMASK(7, 5);
698 ret = regmap_write(base, 0x004, tmp);
699 if (ret)
700 return ret;
701
702 ret = regmap_read(base, 0x008, &orig);
703 if (ret)
704 return ret;
705 tmp = orig & ~BIT(0);
706 tmp |= 0x1 & BIT(0);
707 ret = regmap_write(base, 0x008, tmp);
708 if (ret)
709 return ret;
710
711 /* Enable host port pre-emphasis during non-chirp phase */
712 ret = regmap_read(base, 0x400, &orig);
713 if (ret)
714 return ret;
715 tmp = orig & ~GENMASK(2, 0);
716 tmp |= BIT(2) & GENMASK(2, 0);
717 ret = regmap_write(base, 0x400, tmp);
718 if (ret)
719 return ret;
720
721 /* Set host port squelch trigger point configure to 100mv */
722 ret = regmap_read(base, 0x404, &orig);
723 if (ret)
724 return ret;
725 tmp = orig & ~GENMASK(7, 5);
726 tmp |= 0x40 & GENMASK(7, 5);
727 ret = regmap_write(base, 0x404, tmp);
728 if (ret)
729 return ret;
730
731 ret = regmap_read(base, 0x408, &orig);
732 if (ret)
733 return ret;
734 tmp = orig & ~BIT(0);
735 tmp |= 0x1 & BIT(0);
736 ret = regmap_write(base, 0x408, tmp);
737 if (ret)
738 return ret;
739 }
740
741 return 0;
742 }
743
rk3328_usb2phy_tuning(struct rockchip_usb2phy * rphy)744 static int rk3328_usb2phy_tuning(struct rockchip_usb2phy *rphy)
745 {
746 struct regmap *base = get_reg_base(rphy);
747 unsigned int tmp, orig;
748 int ret;
749
750 if (soc_is_px30s()) {
751 /* Enable otg/host port pre-emphasis during non-chirp phase */
752 ret = regmap_read(base, 0x8000, &orig);
753 if (ret)
754 return ret;
755 tmp = orig & ~GENMASK(2, 0);
756 tmp |= BIT(2) & GENMASK(2, 0);
757 ret = regmap_write(base, 0x8000, tmp);
758 if (ret)
759 return ret;
760
761 /* Set otg port squelch trigger point configure to 100mv */
762 ret = regmap_read(base, 0x8004, &orig);
763 if (ret)
764 return ret;
765 tmp = orig & ~GENMASK(7, 5);
766 tmp |= 0x40 & GENMASK(7, 5);
767 ret = regmap_write(base, 0x8004, tmp);
768 if (ret)
769 return ret;
770
771 ret = regmap_read(base, 0x8008, &orig);
772 if (ret)
773 return ret;
774 tmp = orig & ~BIT(0);
775 tmp |= 0x1 & BIT(0);
776 ret = regmap_write(base, 0x8008, tmp);
777 if (ret)
778 return ret;
779
780 /* Enable host port pre-emphasis during non-chirp phase */
781 ret = regmap_read(base, 0x8400, &orig);
782 if (ret)
783 return ret;
784 tmp = orig & ~GENMASK(2, 0);
785 tmp |= BIT(2) & GENMASK(2, 0);
786 ret = regmap_write(base, 0x8400, tmp);
787 if (ret)
788 return ret;
789
790 /* Set host port squelch trigger point configure to 100mv */
791 ret = regmap_read(base, 0x8404, &orig);
792 if (ret)
793 return ret;
794 tmp = orig & ~GENMASK(7, 5);
795 tmp |= 0x40 & GENMASK(7, 5);
796 ret = regmap_write(base, 0x8404, tmp);
797 if (ret)
798 return ret;
799
800 ret = regmap_read(base, 0x8408, &orig);
801 if (ret)
802 return ret;
803 tmp = orig & ~BIT(0);
804 tmp |= 0x1 & BIT(0);
805 ret = regmap_write(base, 0x8408, tmp);
806 if (ret)
807 return ret;
808 }
809
810 return 0;
811 }
812
rv1106_usb2phy_tuning(struct rockchip_usb2phy * rphy)813 static int rv1106_usb2phy_tuning(struct rockchip_usb2phy *rphy)
814 {
815 u32 reg;
816
817 /* Set HS disconnect detect mode to single ended detect mode */
818 reg = readl(rphy->phy_base + 0x70);
819 writel(reg | BIT(2), rphy->phy_base + 0x70);
820
821 return 0;
822 }
823
rk3528_usb2phy_tuning(struct rockchip_usb2phy * rphy)824 static int rk3528_usb2phy_tuning(struct rockchip_usb2phy *rphy)
825 {
826 u32 reg;
827 int ret = 0;
828
829 if (IS_ERR(rphy->phy_base)) {
830 return PTR_ERR(rphy->phy_base);
831 }
832
833 /* Turn off otg port differential receiver in suspend mode */
834 reg = readl(rphy->phy_base + 0x30);
835 writel(reg & ~BIT(2), rphy->phy_base + 0x30);
836
837 /* Turn off host port differential receiver in suspend mode */
838 reg = readl(rphy->phy_base + 0x0430);
839 writel(reg & ~BIT(2), rphy->phy_base + 0x0430);
840
841 /* Set otg port HS eye height to 400mv(default is 450mv) */
842 reg = readl(rphy->phy_base + 0x30);
843 reg &= ~GENMASK(6, 4);
844 reg |= (0x00 << 4);
845 writel(reg, rphy->phy_base + 0x30);
846
847 /* Set host port HS eye height to 400mv(default is 450mv) */
848 reg = readl(rphy->phy_base + 0x430);
849 reg &= ~GENMASK(6, 4);
850 reg |= (0x00 << 4);
851 writel(reg, rphy->phy_base + 0x430);
852
853 /* Choose the Tx fs/ls data as linestate from TX driver for otg port */
854 reg = readl(rphy->phy_base + 0x94);
855 reg &= ~GENMASK(6, 3);
856 reg |= (0x03 << 3);
857 writel(reg, rphy->phy_base + 0x94);
858
859 /* Turn on output clk of phy*/
860 reg = readl(rphy->phy_base + 0x41c);
861 reg &= ~GENMASK(7, 2);
862 reg |= (0x27 << 2);
863 writel(reg, rphy->phy_base + 0x41c);
864
865 return ret;
866 }
867
rk3562_usb2phy_tuning(struct rockchip_usb2phy * rphy)868 static int rk3562_usb2phy_tuning(struct rockchip_usb2phy *rphy)
869 {
870 u32 reg;
871 int ret = 0;
872
873 if (IS_ERR(rphy->phy_base)) {
874 return PTR_ERR(rphy->phy_base);
875 }
876
877 /* Turn off differential receiver by default to save power */
878 reg = readl(rphy->phy_base + 0x30);
879 writel(reg & ~BIT(2), rphy->phy_base + 0x30);
880
881 reg = readl(rphy->phy_base + 0x0430);
882 writel(reg & ~BIT(2), rphy->phy_base + 0x0430);
883
884 /* Enable pre-emphasis during non-chirp phase */
885 reg = readl(rphy->phy_base);
886 reg &= ~GENMASK(2, 0);
887 reg |= 0x04;
888 writel(reg, rphy->phy_base);
889
890 reg = readl(rphy->phy_base + 0x0400);
891 reg &= ~GENMASK(2, 0);
892 reg |= 0x04;
893 writel(reg, rphy->phy_base + 0x0400);
894
895 /* Set HS eye height to 425mv(default is 400mv) */
896 reg = readl(rphy->phy_base + 0x0030);
897 reg &= ~GENMASK(6, 4);
898 reg |= (0x05 << 4);
899 writel(reg, rphy->phy_base + 0x0030);
900
901 reg = readl(rphy->phy_base + 0x0430);
902 reg &= ~GENMASK(6, 4);
903 reg |= (0x05 << 4);
904 writel(reg, rphy->phy_base + 0x0430);
905
906 return ret;
907 }
908
rk3588_usb2phy_tuning(struct rockchip_usb2phy * rphy)909 static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy)
910 {
911 struct regmap *base = get_reg_base(rphy);
912 int ret;
913
914 /* Deassert SIDDQ to power on analog block */
915 ret = regmap_write(base, 0x0008, GENMASK(29, 29) | 0x0000);
916 if (ret)
917 return ret;
918
919 /* Do reset after exit IDDQ mode */
920 ret = rockchip_usb2phy_reset(rphy);
921 if (ret)
922 return ret;
923
924 /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */
925 ret = regmap_write(base, 0x0004, GENMASK(27, 24) | 0x0900);
926 if (ret)
927 return ret;
928
929 /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */
930 ret = regmap_write(base, 0x0008, GENMASK(20, 19) | 0x0010);
931 if (ret)
932 return ret;
933
934 return 0;
935 }
936
937 static struct phy_ops rockchip_usb2phy_ops = {
938 .init = rockchip_usb2phy_init,
939 .exit = rockchip_usb2phy_exit,
940 .power_on = rockchip_usb2phy_power_on,
941 .power_off = rockchip_usb2phy_power_off,
942 .of_xlate = rockchip_usb2phy_of_xlate,
943 };
944
945 static const struct rockchip_usb2phy_cfg rk1808_phy_cfgs[] = {
946 {
947 .reg = 0x100,
948 .num_ports = 2,
949 .clkout_ctl = { 0x108, 4, 4, 1, 0 },
950 .port_cfgs = {
951 [USB2PHY_PORT_OTG] = {
952 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 },
953 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 },
954 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 },
955 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
956 .iddig_output = { 0x0100, 10, 10, 0, 1 },
957 .iddig_en = { 0x0100, 9, 9, 0, 1 },
958 .idfall_det_en = { 0x0110, 5, 5, 0, 1 },
959 .idfall_det_st = { 0x0114, 5, 5, 0, 1 },
960 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 },
961 .idrise_det_en = { 0x0110, 4, 4, 0, 1 },
962 .idrise_det_st = { 0x0114, 4, 4, 0, 1 },
963 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 },
964 .ls_det_en = { 0x0110, 0, 0, 0, 1 },
965 .ls_det_st = { 0x0114, 0, 0, 0, 1 },
966 .ls_det_clr = { 0x0118, 0, 0, 0, 1 },
967 .utmi_avalid = { 0x0120, 10, 10, 0, 1 },
968 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
969 .utmi_iddig = { 0x0120, 6, 6, 0, 1 },
970 .utmi_ls = { 0x0120, 5, 4, 0, 1 },
971 .vbus_det_en = { 0x001c, 15, 15, 1, 0 },
972 },
973 [USB2PHY_PORT_HOST] = {
974 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 },
975 .ls_det_en = { 0x110, 1, 1, 0, 1 },
976 .ls_det_st = { 0x114, 1, 1, 0, 1 },
977 .ls_det_clr = { 0x118, 1, 1, 0, 1 },
978 .utmi_ls = { 0x120, 17, 16, 0, 1 },
979 .utmi_hstdet = { 0x120, 19, 19, 0, 1 }
980 }
981 },
982 .chg_det = {
983 .opmode = { 0x0100, 3, 0, 5, 1 },
984 .cp_det = { 0x0120, 24, 24, 0, 1 },
985 .dcp_det = { 0x0120, 23, 23, 0, 1 },
986 .dp_det = { 0x0120, 25, 25, 0, 1 },
987 .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
988 .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
989 .idp_src_en = { 0x0108, 9, 9, 0, 1 },
990 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
991 .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
992 .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
993 },
994 },
995 { /* sentinel */ }
996 };
997
998 static const struct rockchip_usb2phy_cfg rk3036_phy_cfgs[] = {
999 {
1000 .reg = 0x17c,
1001 .num_ports = 2,
1002 .clkout_ctl = { 0x017c, 11, 11, 1, 0 },
1003 .port_cfgs = {
1004 [USB2PHY_PORT_OTG] = {
1005 .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 },
1006 .bvalid_det_en = { 0x017c, 14, 14, 0, 1 },
1007 .bvalid_det_st = { 0x017c, 15, 15, 0, 1 },
1008 .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 },
1009 .iddig_output = { 0x017c, 10, 10, 0, 1 },
1010 .iddig_en = { 0x017c, 9, 9, 0, 1 },
1011 .idfall_det_en = { 0x01a0, 2, 2, 0, 1 },
1012 .idfall_det_st = { 0x01a0, 3, 3, 0, 1 },
1013 .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 },
1014 .idrise_det_en = { 0x01a0, 0, 0, 0, 1 },
1015 .idrise_det_st = { 0x01a0, 1, 1, 0, 1 },
1016 .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 },
1017 .ls_det_en = { 0x017c, 12, 12, 0, 1 },
1018 .ls_det_st = { 0x017c, 13, 13, 0, 1 },
1019 .ls_det_clr = { 0x017c, 13, 13, 0, 1 },
1020 .utmi_bvalid = { 0x014c, 5, 5, 0, 1 },
1021 .utmi_iddig = { 0x014c, 8, 8, 0, 1 },
1022 .utmi_ls = { 0x014c, 7, 6, 0, 1 },
1023 },
1024 [USB2PHY_PORT_HOST] = {
1025 .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 },
1026 .ls_det_en = { 0x0194, 14, 14, 0, 1 },
1027 .ls_det_st = { 0x0194, 15, 15, 0, 1 },
1028 .ls_det_clr = { 0x0194, 15, 15, 0, 1 }
1029 }
1030 },
1031 },
1032 { /* sentinel */ }
1033 };
1034
1035 static const struct rockchip_usb2phy_cfg rk312x_phy_cfgs[] = {
1036 {
1037 .reg = 0x17c,
1038 .num_ports = 2,
1039 .clkout_ctl = { 0x0190, 15, 15, 1, 0 },
1040 .port_cfgs = {
1041 [USB2PHY_PORT_OTG] = {
1042 .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 },
1043 .bvalid_det_en = { 0x017c, 14, 14, 0, 1 },
1044 .bvalid_det_st = { 0x017c, 15, 15, 0, 1 },
1045 .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 },
1046 .iddig_output = { 0x017c, 10, 10, 0, 1 },
1047 .iddig_en = { 0x017c, 9, 9, 0, 1 },
1048 .idfall_det_en = { 0x01a0, 2, 2, 0, 1 },
1049 .idfall_det_st = { 0x01a0, 3, 3, 0, 1 },
1050 .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 },
1051 .idrise_det_en = { 0x01a0, 0, 0, 0, 1 },
1052 .idrise_det_st = { 0x01a0, 1, 1, 0, 1 },
1053 .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 },
1054 .ls_det_en = { 0x017c, 12, 12, 0, 1 },
1055 .ls_det_st = { 0x017c, 13, 13, 0, 1 },
1056 .ls_det_clr = { 0x017c, 13, 13, 0, 1 },
1057 .utmi_bvalid = { 0x014c, 5, 5, 0, 1 },
1058 .utmi_iddig = { 0x014c, 8, 8, 0, 1 },
1059 .utmi_ls = { 0x014c, 7, 6, 0, 1 },
1060 },
1061 [USB2PHY_PORT_HOST] = {
1062 .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 },
1063 .ls_det_en = { 0x0194, 14, 14, 0, 1 },
1064 .ls_det_st = { 0x0194, 15, 15, 0, 1 },
1065 .ls_det_clr = { 0x0194, 15, 15, 0, 1 }
1066 }
1067 },
1068 .chg_det = {
1069 .opmode = { 0x017c, 3, 0, 5, 1 },
1070 .cp_det = { 0x02c0, 6, 6, 0, 1 },
1071 .dcp_det = { 0x02c0, 5, 5, 0, 1 },
1072 .dp_det = { 0x02c0, 7, 7, 0, 1 },
1073 .idm_sink_en = { 0x0184, 8, 8, 0, 1 },
1074 .idp_sink_en = { 0x0184, 7, 7, 0, 1 },
1075 .idp_src_en = { 0x0184, 9, 9, 0, 1 },
1076 .rdm_pdwn_en = { 0x0184, 10, 10, 0, 1 },
1077 .vdm_src_en = { 0x0184, 12, 12, 0, 1 },
1078 .vdp_src_en = { 0x0184, 11, 11, 0, 1 },
1079 },
1080 },
1081 { /* sentinel */ }
1082 };
1083
1084 static const struct rockchip_usb2phy_cfg rk322x_phy_cfgs[] = {
1085 {
1086 .reg = 0x760,
1087 .num_ports = 2,
1088 .phy_tuning = rk322x_usb2phy_tuning,
1089 .clkout_ctl = { 0x0768, 4, 4, 1, 0 },
1090 .port_cfgs = {
1091 [USB2PHY_PORT_OTG] = {
1092 .phy_sus = { 0x0760, 8, 0, 0, 0x1d1 },
1093 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 },
1094 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 },
1095 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
1096 .iddig_output = { 0x0760, 10, 10, 0, 1 },
1097 .iddig_en = { 0x0760, 9, 9, 0, 1 },
1098 .idfall_det_en = { 0x0680, 6, 6, 0, 1 },
1099 .idfall_det_st = { 0x0690, 6, 6, 0, 1 },
1100 .idfall_det_clr = { 0x06a0, 6, 6, 0, 1 },
1101 .idrise_det_en = { 0x0680, 5, 5, 0, 1 },
1102 .idrise_det_st = { 0x0690, 5, 5, 0, 1 },
1103 .idrise_det_clr = { 0x06a0, 5, 5, 0, 1 },
1104 .ls_det_en = { 0x0680, 2, 2, 0, 1 },
1105 .ls_det_st = { 0x0690, 2, 2, 0, 1 },
1106 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 },
1107 .utmi_bvalid = { 0x0480, 4, 4, 0, 1 },
1108 .utmi_iddig = { 0x0480, 1, 1, 0, 1 },
1109 .utmi_ls = { 0x0480, 3, 2, 0, 1 },
1110 .vbus_det_en = { 0x0788, 15, 15, 1, 0 },
1111 },
1112 [USB2PHY_PORT_HOST] = {
1113 .phy_sus = { 0x0764, 8, 0, 0, 0x1d1 },
1114 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1115 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1116 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }
1117 }
1118 },
1119 .chg_det = {
1120 .opmode = { 0x0760, 3, 0, 5, 1 },
1121 .cp_det = { 0x0884, 4, 4, 0, 1 },
1122 .dcp_det = { 0x0884, 3, 3, 0, 1 },
1123 .dp_det = { 0x0884, 5, 5, 0, 1 },
1124 .idm_sink_en = { 0x0768, 8, 8, 0, 1 },
1125 .idp_sink_en = { 0x0768, 7, 7, 0, 1 },
1126 .idp_src_en = { 0x0768, 9, 9, 0, 1 },
1127 .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 },
1128 .vdm_src_en = { 0x0768, 12, 12, 0, 1 },
1129 .vdp_src_en = { 0x0768, 11, 11, 0, 1 },
1130 },
1131 },
1132 {
1133 .reg = 0x800,
1134 .num_ports = 2,
1135 .clkout_ctl = { 0x0808, 4, 4, 1, 0 },
1136 .port_cfgs = {
1137 [USB2PHY_PORT_OTG] = {
1138 .phy_sus = { 0x804, 8, 0, 0, 0x1d1 },
1139 .ls_det_en = { 0x0684, 1, 1, 0, 1 },
1140 .ls_det_st = { 0x0694, 1, 1, 0, 1 },
1141 .ls_det_clr = { 0x06a4, 1, 1, 0, 1 }
1142 },
1143 [USB2PHY_PORT_HOST] = {
1144 .phy_sus = { 0x800, 8, 0, 0, 0x1d1 },
1145 .ls_det_en = { 0x0684, 0, 0, 0, 1 },
1146 .ls_det_st = { 0x0694, 0, 0, 0, 1 },
1147 .ls_det_clr = { 0x06a4, 0, 0, 0, 1 }
1148 }
1149 },
1150 },
1151 { /* sentinel */ }
1152 };
1153
1154 static const struct rockchip_usb2phy_cfg rk3308_phy_cfgs[] = {
1155 {
1156 .reg = 0x100,
1157 .num_ports = 2,
1158 .phy_tuning = rk3308_usb2phy_tuning,
1159 .clkout_ctl = { 0x0108, 4, 4, 1, 0 },
1160 .port_cfgs = {
1161 [USB2PHY_PORT_OTG] = {
1162 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 },
1163 .bvalid_det_en = { 0x3020, 2, 2, 0, 1 },
1164 .bvalid_det_st = { 0x3024, 2, 2, 0, 1 },
1165 .bvalid_det_clr = { 0x3028, 2, 2, 0, 1 },
1166 .iddig_output = { 0x0100, 10, 10, 0, 1 },
1167 .iddig_en = { 0x0100, 9, 9, 0, 1 },
1168 .idfall_det_en = { 0x3020, 5, 5, 0, 1 },
1169 .idfall_det_st = { 0x3024, 5, 5, 0, 1 },
1170 .idfall_det_clr = { 0x3028, 5, 5, 0, 1 },
1171 .idrise_det_en = { 0x3020, 4, 4, 0, 1 },
1172 .idrise_det_st = { 0x3024, 4, 4, 0, 1 },
1173 .idrise_det_clr = { 0x3028, 4, 4, 0, 1 },
1174 .ls_det_en = { 0x3020, 0, 0, 0, 1 },
1175 .ls_det_st = { 0x3024, 0, 0, 0, 1 },
1176 .ls_det_clr = { 0x3028, 0, 0, 0, 1 },
1177 .utmi_avalid = { 0x0120, 10, 10, 0, 1 },
1178 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
1179 .utmi_iddig = { 0x0120, 6, 6, 0, 1 },
1180 .utmi_ls = { 0x0120, 5, 4, 0, 1 },
1181 .vbus_det_en = { 0x001c, 15, 15, 1, 0 },
1182 },
1183 [USB2PHY_PORT_HOST] = {
1184 .phy_sus = { 0x0104, 8, 0, 0, 0x1d1 },
1185 .ls_det_en = { 0x3020, 1, 1, 0, 1 },
1186 .ls_det_st = { 0x3024, 1, 1, 0, 1 },
1187 .ls_det_clr = { 0x3028, 1, 1, 0, 1 },
1188 .utmi_ls = { 0x120, 17, 16, 0, 1 },
1189 .utmi_hstdet = { 0x120, 19, 19, 0, 1 }
1190 }
1191 },
1192 .chg_det = {
1193 .opmode = { 0x0100, 3, 0, 5, 1 },
1194 .cp_det = { 0x0120, 24, 24, 0, 1 },
1195 .dcp_det = { 0x0120, 23, 23, 0, 1 },
1196 .dp_det = { 0x0120, 25, 25, 0, 1 },
1197 .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
1198 .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
1199 .idp_src_en = { 0x0108, 9, 9, 0, 1 },
1200 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
1201 .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
1202 .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
1203 },
1204 },
1205 { /* sentinel */ }
1206 };
1207
1208 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
1209 {
1210 .reg = 0x100,
1211 .num_ports = 2,
1212 .phy_tuning = rk3328_usb2phy_tuning,
1213 .clkout_ctl = { 0x108, 4, 4, 1, 0 },
1214 .port_cfgs = {
1215 [USB2PHY_PORT_OTG] = {
1216 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 },
1217 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 },
1218 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 },
1219 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
1220 .iddig_output = { 0x0100, 10, 10, 0, 1 },
1221 .iddig_en = { 0x0100, 9, 9, 0, 1 },
1222 .idfall_det_en = { 0x0110, 5, 5, 0, 1 },
1223 .idfall_det_st = { 0x0114, 5, 5, 0, 1 },
1224 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 },
1225 .idrise_det_en = { 0x0110, 4, 4, 0, 1 },
1226 .idrise_det_st = { 0x0114, 4, 4, 0, 1 },
1227 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 },
1228 .ls_det_en = { 0x0110, 0, 0, 0, 1 },
1229 .ls_det_st = { 0x0114, 0, 0, 0, 1 },
1230 .ls_det_clr = { 0x0118, 0, 0, 0, 1 },
1231 .utmi_avalid = { 0x0120, 10, 10, 0, 1 },
1232 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
1233 .utmi_iddig = { 0x0120, 6, 6, 0, 1 },
1234 .utmi_ls = { 0x0120, 5, 4, 0, 1 },
1235 .vbus_det_en = { 0x001c, 15, 15, 1, 0 },
1236 },
1237 [USB2PHY_PORT_HOST] = {
1238 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 },
1239 .ls_det_en = { 0x110, 1, 1, 0, 1 },
1240 .ls_det_st = { 0x114, 1, 1, 0, 1 },
1241 .ls_det_clr = { 0x118, 1, 1, 0, 1 },
1242 .utmi_ls = { 0x120, 17, 16, 0, 1 },
1243 .utmi_hstdet = { 0x120, 19, 19, 0, 1 }
1244 }
1245 },
1246 .chg_det = {
1247 .opmode = { 0x0100, 3, 0, 5, 1 },
1248 .cp_det = { 0x0120, 24, 24, 0, 1 },
1249 .dcp_det = { 0x0120, 23, 23, 0, 1 },
1250 .dp_det = { 0x0120, 25, 25, 0, 1 },
1251 .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
1252 .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
1253 .idp_src_en = { 0x0108, 9, 9, 0, 1 },
1254 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
1255 .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
1256 .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
1257 },
1258 },
1259 { /* sentinel */ }
1260 };
1261
1262 static const struct rockchip_usb2phy_cfg rk3368_phy_cfgs[] = {
1263 {
1264 .reg = 0x700,
1265 .num_ports = 2,
1266 .clkout_ctl = { 0x0724, 15, 15, 1, 0 },
1267 .port_cfgs = {
1268 [USB2PHY_PORT_OTG] = {
1269 .phy_sus = { 0x0700, 8, 0, 0, 0x1d1 },
1270 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 },
1271 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 },
1272 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
1273 .ls_det_en = { 0x0680, 2, 2, 0, 1 },
1274 .ls_det_st = { 0x0690, 2, 2, 0, 1 },
1275 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 },
1276 .utmi_bvalid = { 0x04bc, 23, 23, 0, 1 },
1277 .utmi_ls = { 0x04bc, 25, 24, 0, 1 },
1278 },
1279 [USB2PHY_PORT_HOST] = {
1280 .phy_sus = { 0x0728, 8, 0, 0, 0x1d1 },
1281 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1282 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1283 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }
1284 }
1285 },
1286 .chg_det = {
1287 .opmode = { 0x0700, 3, 0, 5, 1 },
1288 .cp_det = { 0x04b8, 30, 30, 0, 1 },
1289 .dcp_det = { 0x04b8, 29, 29, 0, 1 },
1290 .dp_det = { 0x04b8, 31, 31, 0, 1 },
1291 .idm_sink_en = { 0x0718, 8, 8, 0, 1 },
1292 .idp_sink_en = { 0x0718, 7, 7, 0, 1 },
1293 .idp_src_en = { 0x0718, 9, 9, 0, 1 },
1294 .rdm_pdwn_en = { 0x0718, 10, 10, 0, 1 },
1295 .vdm_src_en = { 0x0718, 12, 12, 0, 1 },
1296 .vdp_src_en = { 0x0718, 11, 11, 0, 1 },
1297 },
1298 },
1299 { /* sentinel */ }
1300 };
1301
1302 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
1303 {
1304 .reg = 0xe450,
1305 .num_ports = 2,
1306 .clkout_ctl = { 0xe450, 4, 4, 1, 0 },
1307 .port_cfgs = {
1308 [USB2PHY_PORT_OTG] = {
1309 .phy_sus = { 0xe454, 8, 0, 0x052, 0x1d1 },
1310 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 },
1311 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 },
1312 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
1313 .idfall_det_en = { 0xe3c0, 5, 5, 0, 1 },
1314 .idfall_det_st = { 0xe3e0, 5, 5, 0, 1 },
1315 .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 },
1316 .idrise_det_en = { 0xe3c0, 4, 4, 0, 1 },
1317 .idrise_det_st = { 0xe3e0, 4, 4, 0, 1 },
1318 .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 },
1319 .ls_det_en = { 0xe3c0, 2, 2, 0, 1 },
1320 .ls_det_st = { 0xe3e0, 2, 2, 0, 1 },
1321 .ls_det_clr = { 0xe3d0, 2, 2, 0, 1 },
1322 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 },
1323 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 },
1324 .utmi_iddig = { 0xe2ac, 8, 8, 0, 1 },
1325 .utmi_ls = { 0xe2ac, 14, 13, 0, 1 },
1326 .vbus_det_en = { 0x449c, 15, 15, 1, 0 },
1327 },
1328 [USB2PHY_PORT_HOST] = {
1329 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 },
1330 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 },
1331 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 },
1332 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 },
1333 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 },
1334 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 }
1335 }
1336 },
1337 .chg_det = {
1338 .opmode = { 0xe454, 3, 0, 5, 1 },
1339 .cp_det = { 0xe2ac, 2, 2, 0, 1 },
1340 .dcp_det = { 0xe2ac, 1, 1, 0, 1 },
1341 .dp_det = { 0xe2ac, 0, 0, 0, 1 },
1342 .idm_sink_en = { 0xe450, 8, 8, 0, 1 },
1343 .idp_sink_en = { 0xe450, 7, 7, 0, 1 },
1344 .idp_src_en = { 0xe450, 9, 9, 0, 1 },
1345 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 },
1346 .vdm_src_en = { 0xe450, 12, 12, 0, 1 },
1347 .vdp_src_en = { 0xe450, 11, 11, 0, 1 },
1348 },
1349 },
1350 {
1351 .reg = 0xe460,
1352 .num_ports = 2,
1353 .clkout_ctl = { 0xe460, 4, 4, 1, 0 },
1354 .port_cfgs = {
1355 [USB2PHY_PORT_OTG] = {
1356 .phy_sus = { 0xe464, 8, 0, 0x052, 0x1d1 },
1357 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 },
1358 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 },
1359 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
1360 .idfall_det_en = { 0xe3c0, 10, 10, 0, 1 },
1361 .idfall_det_st = { 0xe3e0, 10, 10, 0, 1 },
1362 .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 },
1363 .idrise_det_en = { 0xe3c0, 9, 9, 0, 1 },
1364 .idrise_det_st = { 0xe3e0, 9, 9, 0, 1 },
1365 .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 },
1366 .ls_det_en = { 0xe3c0, 7, 7, 0, 1 },
1367 .ls_det_st = { 0xe3e0, 7, 7, 0, 1 },
1368 .ls_det_clr = { 0xe3d0, 7, 7, 0, 1 },
1369 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 },
1370 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 },
1371 .utmi_iddig = { 0xe2ac, 11, 11, 0, 1 },
1372 .utmi_ls = { 0xe2ac, 18, 17, 0, 1 },
1373 .vbus_det_en = { 0x451c, 15, 15, 1, 0 },
1374 },
1375 [USB2PHY_PORT_HOST] = {
1376 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 },
1377 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 },
1378 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 },
1379 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 },
1380 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 },
1381 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 }
1382 }
1383 },
1384 .chg_det = {
1385 .opmode = { 0xe464, 3, 0, 5, 1 },
1386 .cp_det = { 0xe2ac, 5, 5, 0, 1 },
1387 .dcp_det = { 0xe2ac, 4, 4, 0, 1 },
1388 .dp_det = { 0xe2ac, 3, 3, 0, 1 },
1389 .idm_sink_en = { 0xe460, 8, 8, 0, 1 },
1390 .idp_sink_en = { 0xe460, 7, 7, 0, 1 },
1391 .idp_src_en = { 0xe460, 9, 9, 0, 1 },
1392 .rdm_pdwn_en = { 0xe460, 10, 10, 0, 1 },
1393 .vdm_src_en = { 0xe460, 12, 12, 0, 1 },
1394 .vdp_src_en = { 0xe460, 11, 11, 0, 1 },
1395 },
1396 },
1397 { /* sentinel */ }
1398 };
1399
1400 static const struct rockchip_usb2phy_cfg rv1106_phy_cfgs[] = {
1401 {
1402 .reg = 0xff3e0000,
1403 .num_ports = 1,
1404 .phy_tuning = rv1106_usb2phy_tuning,
1405 .clkout_ctl = { 0x0058, 4, 4, 1, 0 },
1406 .port_cfgs = {
1407 [USB2PHY_PORT_OTG] = {
1408 .phy_sus = { 0x0050, 8, 0, 0, 0x1d1 },
1409 .bvalid_det_en = { 0x0100, 2, 2, 0, 1 },
1410 .bvalid_det_st = { 0x0104, 2, 2, 0, 1 },
1411 .bvalid_det_clr = { 0x0108, 2, 2, 0, 1 },
1412 .iddig_output = { 0x0050, 10, 10, 0, 1 },
1413 .iddig_en = { 0x0050, 9, 9, 0, 1 },
1414 .idfall_det_en = { 0x0100, 5, 5, 0, 1 },
1415 .idfall_det_st = { 0x0104, 5, 5, 0, 1 },
1416 .idfall_det_clr = { 0x0108, 5, 5, 0, 1 },
1417 .idrise_det_en = { 0x0100, 4, 4, 0, 1 },
1418 .idrise_det_st = { 0x0104, 4, 4, 0, 1 },
1419 .idrise_det_clr = { 0x0108, 4, 4, 0, 1 },
1420 .ls_det_en = { 0x0100, 0, 0, 0, 1 },
1421 .ls_det_st = { 0x0104, 0, 0, 0, 1 },
1422 .ls_det_clr = { 0x0108, 0, 0, 0, 1 },
1423 .utmi_avalid = { 0x0060, 10, 10, 0, 1 },
1424 .utmi_bvalid = { 0x0060, 9, 9, 0, 1 },
1425 .utmi_iddig = { 0x0060, 6, 6, 0, 1 },
1426 .utmi_ls = { 0x0060, 5, 4, 0, 1 },
1427 },
1428 },
1429 .chg_det = {
1430 .opmode = { 0x0050, 3, 0, 5, 1 },
1431 .cp_det = { 0x0060, 13, 13, 0, 1 },
1432 .dcp_det = { 0x0060, 12, 12, 0, 1 },
1433 .dp_det = { 0x0060, 14, 14, 0, 1 },
1434 .idm_sink_en = { 0x0058, 8, 8, 0, 1 },
1435 .idp_sink_en = { 0x0058, 7, 7, 0, 1 },
1436 .idp_src_en = { 0x0058, 9, 9, 0, 1 },
1437 .rdm_pdwn_en = { 0x0058, 10, 10, 0, 1 },
1438 .vdm_src_en = { 0x0058, 12, 12, 0, 1 },
1439 .vdp_src_en = { 0x0058, 11, 11, 0, 1 },
1440 },
1441 },
1442 { /* sentinel */ }
1443 };
1444
1445 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
1446 {
1447 .reg = 0x100,
1448 .num_ports = 2,
1449 .clkout_ctl = { 0x108, 4, 4, 1, 0 },
1450 .port_cfgs = {
1451 [USB2PHY_PORT_OTG] = {
1452 .phy_sus = { 0x0ffa0100, 8, 0, 0, 0x1d1 },
1453 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 },
1454 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 },
1455 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
1456 .ls_det_en = { 0x0680, 2, 2, 0, 1 },
1457 .ls_det_st = { 0x0690, 2, 2, 0, 1 },
1458 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 },
1459 .utmi_bvalid = { 0x0804, 10, 10, 0, 1 },
1460 .utmi_ls = { 0x0804, 13, 12, 0, 1 },
1461 },
1462 [USB2PHY_PORT_HOST] = {
1463 .phy_sus = { 0x0ffa0104, 8, 0, 0, 0x1d1 },
1464 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1465 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1466 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 },
1467 .utmi_ls = { 0x0804, 9, 8, 0, 1 },
1468 .utmi_hstdet = { 0x0804, 7, 7, 0, 1 }
1469 }
1470 },
1471 .chg_det = {
1472 .opmode = { 0x0ffa0100, 3, 0, 5, 1 },
1473 .cp_det = { 0x0804, 1, 1, 0, 1 },
1474 .dcp_det = { 0x0804, 0, 0, 0, 1 },
1475 .dp_det = { 0x0804, 2, 2, 0, 1 },
1476 .idm_sink_en = { 0x0ffa0108, 8, 8, 0, 1 },
1477 .idp_sink_en = { 0x0ffa0108, 7, 7, 0, 1 },
1478 .idp_src_en = { 0x0ffa0108, 9, 9, 0, 1 },
1479 .rdm_pdwn_en = { 0x0ffa0108, 10, 10, 0, 1 },
1480 .vdm_src_en = { 0x0ffa0108, 12, 12, 0, 1 },
1481 .vdp_src_en = { 0x0ffa0108, 11, 11, 0, 1 },
1482 },
1483 },
1484 { /* sentinel */ }
1485 };
1486
1487 static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = {
1488 {
1489 .reg = 0xffdf0000,
1490 .num_ports = 2,
1491 .phy_tuning = rk3528_usb2phy_tuning,
1492 .port_cfgs = {
1493 [USB2PHY_PORT_OTG] = {
1494 .phy_sus = { 0x6004c, 8, 0, 0, 0x1d1 },
1495 .bvalid_det_en = { 0x60074, 2, 2, 0, 1 },
1496 .bvalid_det_st = { 0x60078, 2, 2, 0, 1 },
1497 .bvalid_det_clr = { 0x6007c, 2, 2, 0, 1 },
1498 .iddig_output = { 0x6004c, 10, 10, 0, 1 },
1499 .iddig_en = { 0x6004c, 9, 9, 0, 1 },
1500 .idfall_det_en = { 0x60074, 5, 5, 0, 1 },
1501 .idfall_det_st = { 0x60078, 5, 5, 0, 1 },
1502 .idfall_det_clr = { 0x6007c, 5, 5, 0, 1 },
1503 .idrise_det_en = { 0x60074, 4, 4, 0, 1 },
1504 .idrise_det_st = { 0x60078, 4, 4, 0, 1 },
1505 .idrise_det_clr = { 0x6007c, 4, 4, 0, 1 },
1506 .ls_det_en = { 0x60074, 0, 0, 0, 1 },
1507 .ls_det_st = { 0x60078, 0, 0, 0, 1 },
1508 .ls_det_clr = { 0x6007c, 0, 0, 0, 1 },
1509 .utmi_avalid = { 0x6006c, 1, 1, 0, 1 },
1510 .utmi_bvalid = { 0x6006c, 0, 0, 0, 1 },
1511 .utmi_iddig = { 0x6006c, 6, 6, 0, 1 },
1512 .utmi_ls = { 0x6006c, 5, 4, 0, 1 },
1513 },
1514 [USB2PHY_PORT_HOST] = {
1515 .phy_sus = { 0x6005c, 8, 0, 0x1d2, 0x1d1 },
1516 .ls_det_en = { 0x60090, 0, 0, 0, 1 },
1517 .ls_det_st = { 0x60094, 0, 0, 0, 1 },
1518 .ls_det_clr = { 0x60098, 0, 0, 0, 1 },
1519 .utmi_ls = { 0x6006c, 13, 12, 0, 1 },
1520 .utmi_hstdet = { 0x6006c, 15, 15, 0, 1 }
1521 }
1522 },
1523 .chg_det = {
1524 .opmode = { 0x6004c, 3, 0, 5, 1 },
1525 .cp_det = { 0x6006c, 19, 19, 0, 1 },
1526 .dcp_det = { 0x6006c, 18, 18, 0, 1 },
1527 .dp_det = { 0x6006c, 20, 20, 0, 1 },
1528 .idm_sink_en = { 0x60058, 1, 1, 0, 1 },
1529 .idp_sink_en = { 0x60058, 0, 0, 0, 1 },
1530 .idp_src_en = { 0x60058, 2, 2, 0, 1 },
1531 .rdm_pdwn_en = { 0x60058, 3, 3, 0, 1 },
1532 .vdm_src_en = { 0x60058, 5, 5, 0, 1 },
1533 .vdp_src_en = { 0x60058, 4, 4, 0, 1 },
1534 },
1535 }
1536 };
1537
1538 static const struct rockchip_usb2phy_cfg rk3562_phy_cfgs[] = {
1539 {
1540 .reg = 0xff740000,
1541 .num_ports = 2,
1542 .phy_tuning = rk3562_usb2phy_tuning,
1543 .clkout_ctl = { 0x0108, 4, 4, 1, 0 },
1544 .port_cfgs = {
1545 [USB2PHY_PORT_OTG] = {
1546 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 },
1547 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 },
1548 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 },
1549 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
1550 .iddig_output = { 0x0100, 10, 10, 0, 1 },
1551 .iddig_en = { 0x0100, 9, 9, 0, 1 },
1552 .idfall_det_en = { 0x0110, 5, 5, 0, 1 },
1553 .idfall_det_st = { 0x0114, 5, 5, 0, 1 },
1554 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 },
1555 .idrise_det_en = { 0x0110, 4, 4, 0, 1 },
1556 .idrise_det_st = { 0x0114, 4, 4, 0, 1 },
1557 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 },
1558 .ls_det_en = { 0x0110, 0, 0, 0, 1 },
1559 .ls_det_st = { 0x0114, 0, 0, 0, 1 },
1560 .ls_det_clr = { 0x0118, 0, 0, 0, 1 },
1561 .utmi_avalid = { 0x0120, 10, 10, 0, 1 },
1562 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
1563 .utmi_iddig = { 0x0120, 6, 6, 0, 1 },
1564 .utmi_ls = { 0x0120, 5, 4, 0, 1 },
1565 },
1566 [USB2PHY_PORT_HOST] = {
1567 .phy_sus = { 0x0104, 8, 0, 0x1d2, 0x1d1 },
1568 .ls_det_en = { 0x0110, 1, 1, 0, 1 },
1569 .ls_det_st = { 0x0114, 1, 1, 0, 1 },
1570 .ls_det_clr = { 0x0118, 1, 1, 0, 1 },
1571 .utmi_ls = { 0x0120, 17, 16, 0, 1 },
1572 .utmi_hstdet = { 0x0120, 19, 19, 0, 1 }
1573 }
1574 },
1575 .chg_det = {
1576 .opmode = { 0x0100, 3, 0, 5, 1 },
1577 .cp_det = { 0x0120, 24, 24, 0, 1 },
1578 .dcp_det = { 0x0120, 23, 23, 0, 1 },
1579 .dp_det = { 0x0120, 25, 25, 0, 1 },
1580 .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
1581 .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
1582 .idp_src_en = { 0x0108, 9, 9, 0, 1 },
1583 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
1584 .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
1585 .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
1586 },
1587 },
1588 { /* sentinel */ }
1589 };
1590
1591 static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
1592 {
1593 .reg = 0xfe8a0000,
1594 .num_ports = 2,
1595 .clkout_ctl = { 0x0008, 4, 4, 1, 0 },
1596 .port_cfgs = {
1597 [USB2PHY_PORT_OTG] = {
1598 .phy_sus = { 0x0000, 8, 0, 0x052, 0x1d1 },
1599 .bvalid_det_en = { 0x0080, 2, 2, 0, 1 },
1600 .bvalid_det_st = { 0x0084, 2, 2, 0, 1 },
1601 .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 },
1602 .iddig_output = { 0x0000, 10, 10, 0, 1 },
1603 .iddig_en = { 0x0000, 9, 9, 0, 1 },
1604 .idfall_det_en = { 0x0080, 5, 5, 0, 1 },
1605 .idfall_det_st = { 0x0084, 5, 5, 0, 1 },
1606 .idfall_det_clr = { 0x0088, 5, 5, 0, 1 },
1607 .idrise_det_en = { 0x0080, 4, 4, 0, 1 },
1608 .idrise_det_st = { 0x0084, 4, 4, 0, 1 },
1609 .idrise_det_clr = { 0x0088, 4, 4, 0, 1 },
1610 .ls_det_en = { 0x0080, 0, 0, 0, 1 },
1611 .ls_det_st = { 0x0084, 0, 0, 0, 1 },
1612 .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
1613 .utmi_avalid = { 0x00c0, 10, 10, 0, 1 },
1614 .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 },
1615 .utmi_iddig = { 0x00c0, 6, 6, 0, 1 },
1616 .utmi_ls = { 0x00c0, 5, 4, 0, 1 },
1617 },
1618 [USB2PHY_PORT_HOST] = {
1619 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 },
1620 .ls_det_en = { 0x0080, 1, 1, 0, 1 },
1621 .ls_det_st = { 0x0084, 1, 1, 0, 1 },
1622 .ls_det_clr = { 0x0088, 1, 1, 0, 1 },
1623 .utmi_ls = { 0x00c0, 17, 16, 0, 1 },
1624 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
1625 }
1626 },
1627 .chg_det = {
1628 .opmode = { 0x0000, 3, 0, 5, 1 },
1629 .cp_det = { 0x00c0, 24, 24, 0, 1 },
1630 .dcp_det = { 0x00c0, 23, 23, 0, 1 },
1631 .dp_det = { 0x00c0, 25, 25, 0, 1 },
1632 .idm_sink_en = { 0x0008, 8, 8, 0, 1 },
1633 .idp_sink_en = { 0x0008, 7, 7, 0, 1 },
1634 .idp_src_en = { 0x0008, 9, 9, 0, 1 },
1635 .rdm_pdwn_en = { 0x0008, 10, 10, 0, 1 },
1636 .vdm_src_en = { 0x0008, 12, 12, 0, 1 },
1637 .vdp_src_en = { 0x0008, 11, 11, 0, 1 },
1638 },
1639 },
1640 {
1641 .reg = 0xfe8b0000,
1642 .num_ports = 2,
1643 .clkout_ctl = { 0x0008, 4, 4, 1, 0 },
1644 .port_cfgs = {
1645 [USB2PHY_PORT_OTG] = {
1646 .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 },
1647 .ls_det_en = { 0x0080, 0, 0, 0, 1 },
1648 .ls_det_st = { 0x0084, 0, 0, 0, 1 },
1649 .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
1650 .utmi_ls = { 0x00c0, 5, 4, 0, 1 },
1651 .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 }
1652 },
1653 [USB2PHY_PORT_HOST] = {
1654 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 },
1655 .ls_det_en = { 0x0080, 1, 1, 0, 1 },
1656 .ls_det_st = { 0x0084, 1, 1, 0, 1 },
1657 .ls_det_clr = { 0x0088, 1, 1, 0, 1 },
1658 .utmi_ls = { 0x00c0, 17, 16, 0, 1 },
1659 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
1660 }
1661 },
1662 },
1663 { /* sentinel */ }
1664 };
1665
1666 static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {
1667 {
1668 .reg = 0x0000,
1669 .num_ports = 1,
1670 .phy_tuning = rk3588_usb2phy_tuning,
1671 .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
1672 .port_cfgs = {
1673 [USB2PHY_PORT_OTG] = {
1674 .phy_sus = { 0x000c, 11, 11, 0, 1 },
1675 .ls_det_en = { 0x0080, 0, 0, 0, 1 },
1676 .ls_det_st = { 0x0084, 0, 0, 0, 1 },
1677 .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
1678 .utmi_avalid = { 0x00c0, 7, 7, 0, 1 },
1679 .utmi_bvalid = { 0x00c0, 6, 6, 0, 1 },
1680 .utmi_iddig = { 0x00c0, 5, 5, 0, 1 },
1681 .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
1682 }
1683 },
1684 .chg_det = {
1685 .opmode = { 0x0008, 2, 2, 1, 0 },
1686 .cp_det = { 0x00c0, 0, 0, 0, 1 },
1687 .dcp_det = { 0x00c0, 0, 0, 0, 1 },
1688 .dp_det = { 0x00c0, 1, 1, 1, 0 },
1689 .idm_sink_en = { 0x0008, 5, 5, 1, 0 },
1690 .idp_sink_en = { 0x0008, 5, 5, 0, 1 },
1691 .idp_src_en = { 0x0008, 14, 14, 0, 1 },
1692 .rdm_pdwn_en = { 0x0008, 14, 14, 0, 1 },
1693 .vdm_src_en = { 0x0008, 7, 6, 0, 3 },
1694 .vdp_src_en = { 0x0008, 7, 6, 0, 3 },
1695 },
1696 },
1697 {
1698 .reg = 0x4000,
1699 .num_ports = 1,
1700 .phy_tuning = rk3588_usb2phy_tuning,
1701 .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
1702 .port_cfgs = {
1703 /* Select suspend control from controller */
1704 [USB2PHY_PORT_OTG] = {
1705 .phy_sus = { 0x000c, 11, 11, 0, 0 },
1706 .ls_det_en = { 0x0080, 0, 0, 0, 1 },
1707 .ls_det_st = { 0x0084, 0, 0, 0, 1 },
1708 .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
1709 .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
1710 }
1711 },
1712 },
1713 {
1714 .reg = 0x8000,
1715 .num_ports = 1,
1716 .phy_tuning = rk3588_usb2phy_tuning,
1717 .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
1718 .port_cfgs = {
1719 [USB2PHY_PORT_HOST] = {
1720 .phy_sus = { 0x0008, 2, 2, 0, 1 },
1721 .ls_det_en = { 0x0080, 0, 0, 0, 1 },
1722 .ls_det_st = { 0x0084, 0, 0, 0, 1 },
1723 .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
1724 .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
1725 }
1726 },
1727 },
1728 {
1729 .reg = 0xc000,
1730 .num_ports = 1,
1731 .phy_tuning = rk3588_usb2phy_tuning,
1732 .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
1733 .port_cfgs = {
1734 [USB2PHY_PORT_HOST] = {
1735 .phy_sus = { 0x0008, 2, 2, 0, 1 },
1736 .ls_det_en = { 0x0080, 0, 0, 0, 1 },
1737 .ls_det_st = { 0x0084, 0, 0, 0, 1 },
1738 .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
1739 .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
1740 }
1741 },
1742 },
1743 { /* sentinel */ }
1744 };
1745
1746 static const struct udevice_id rockchip_usb2phy_ids[] = {
1747 #ifdef CONFIG_ROCKCHIP_RK1808
1748 { .compatible = "rockchip,rk1808-usb2phy", .data = (ulong)&rk1808_phy_cfgs },
1749 #endif
1750 #ifdef CONFIG_ROCKCHIP_RK3036
1751 { .compatible = "rockchip,rk3036-usb2phy", .data = (ulong)&rk3036_phy_cfgs },
1752 #endif
1753 #if defined CONFIG_ROCKCHIP_RK3128 || defined CONFIG_ROCKCHIP_RK3126
1754 { .compatible = "rockchip,rk3128-usb2phy", .data = (ulong)&rk312x_phy_cfgs },
1755 #endif
1756 #ifdef CONFIG_ROCKCHIP_RK322X
1757 { .compatible = "rockchip,rk322x-usb2phy", .data = (ulong)&rk322x_phy_cfgs },
1758 #endif
1759 #ifdef CONFIG_ROCKCHIP_RK3308
1760 { .compatible = "rockchip,rk3308-usb2phy", .data = (ulong)&rk3308_phy_cfgs },
1761 #endif
1762 #if defined CONFIG_ROCKCHIP_RK3328 || defined CONFIG_ROCKCHIP_PX30
1763 { .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_phy_cfgs },
1764 #endif
1765 #ifdef CONFIG_ROCKCHIP_RK3368
1766 { .compatible = "rockchip,rk3368-usb2phy", .data = (ulong)&rk3368_phy_cfgs },
1767 #endif
1768 #ifdef CONFIG_ROCKCHIP_RK3399
1769 { .compatible = "rockchip,rk3399-usb2phy", .data = (ulong)&rk3399_phy_cfgs },
1770 #endif
1771 #ifdef CONFIG_ROCKCHIP_RK3528
1772 { .compatible = "rockchip,rk3528-usb2phy", .data = (ulong)&rk3528_phy_cfgs },
1773 #endif
1774 #ifdef CONFIG_ROCKCHIP_RK3562
1775 { .compatible = "rockchip,rk3562-usb2phy", .data = (ulong)&rk3562_phy_cfgs },
1776 #endif
1777 #ifdef CONFIG_ROCKCHIP_RK3568
1778 { .compatible = "rockchip,rk3568-usb2phy", .data = (ulong)&rk3568_phy_cfgs },
1779 #endif
1780 #ifdef CONFIG_ROCKCHIP_RK3588
1781 { .compatible = "rockchip,rk3588-usb2phy", .data = (ulong)&rk3588_phy_cfgs },
1782 #endif
1783 #ifdef CONFIG_ROCKCHIP_RV1106
1784 { .compatible = "rockchip,rv1106-usb2phy", .data = (ulong)&rv1106_phy_cfgs },
1785 #endif
1786 #ifdef CONFIG_ROCKCHIP_RV1108
1787 { .compatible = "rockchip,rv1108-usb2phy", .data = (ulong)&rv1108_phy_cfgs },
1788 #endif
1789 { }
1790 };
1791
1792 U_BOOT_DRIVER(rockchip_usb2phy_port) = {
1793 .name = "rockchip_usb2phy_port",
1794 .id = UCLASS_PHY,
1795 .ops = &rockchip_usb2phy_ops,
1796 };
1797
1798 U_BOOT_DRIVER(rockchip_usb2phy) = {
1799 .name = "rockchip_usb2phy",
1800 .id = UCLASS_PHY,
1801 .of_match = rockchip_usb2phy_ids,
1802 .probe = rockchip_usb2phy_probe,
1803 .bind = rockchip_usb2phy_bind,
1804 .priv_auto_alloc_size = sizeof(struct rockchip_usb2phy),
1805 };
1806