1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2015-2016 Marvell International Ltd. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _SATA_H_ 8*4882a593Smuzhiyun #define _SATA_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* SATA3 Unit address */ 11*4882a593Smuzhiyun #define SATA3_VENDOR_ADDRESS 0xA0 12*4882a593Smuzhiyun #define SATA3_VENDOR_ADDR_OFSSET 0 13*4882a593Smuzhiyun #define SATA3_VENDOR_ADDR_MASK (0xFFFFFFFF << SATA3_VENDOR_ADDR_OFSSET) 14*4882a593Smuzhiyun #define SATA3_VENDOR_DATA 0xA4 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define SATA_CONTROL_REG 0x0 17*4882a593Smuzhiyun #define SATA3_CTRL_SATA0_PD_OFFSET 6 18*4882a593Smuzhiyun #define SATA3_CTRL_SATA0_PD_MASK (1 << SATA3_CTRL_SATA0_PD_OFFSET) 19*4882a593Smuzhiyun #define SATA3_CTRL_SATA1_PD_OFFSET 14 20*4882a593Smuzhiyun #define SATA3_CTRL_SATA1_PD_MASK (1 << SATA3_CTRL_SATA1_PD_OFFSET) 21*4882a593Smuzhiyun #define SATA3_CTRL_SATA1_ENABLE_OFFSET 22 22*4882a593Smuzhiyun #define SATA3_CTRL_SATA1_ENABLE_MASK (1 << SATA3_CTRL_SATA1_ENABLE_OFFSET) 23*4882a593Smuzhiyun #define SATA3_CTRL_SATA_SSU_OFFSET 23 24*4882a593Smuzhiyun #define SATA3_CTRL_SATA_SSU_MASK (1 << SATA3_CTRL_SATA_SSU_OFFSET) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define SATA_MBUS_SIZE_SELECT_REG 0x4 27*4882a593Smuzhiyun #define SATA_MBUS_REGRET_EN_OFFSET 7 28*4882a593Smuzhiyun #define SATA_MBUS_REGRET_EN_MASK (0x1 << SATA_MBUS_REGRET_EN_OFFSET) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #endif /* _SATA_H_ */ 31