1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2015-2016 Marvell International Ltd.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #ifndef _COMPHY_H_
8*4882a593Smuzhiyun #define _COMPHY_H_
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <dt-bindings/comphy/comphy_data.h>
11*4882a593Smuzhiyun #include <fdtdec.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #if defined(DEBUG)
14*4882a593Smuzhiyun #define debug_enter() printf("----> Enter %s\n", __func__);
15*4882a593Smuzhiyun #define debug_exit() printf("<---- Exit %s\n", __func__);
16*4882a593Smuzhiyun #else
17*4882a593Smuzhiyun #define debug_enter()
18*4882a593Smuzhiyun #define debug_exit()
19*4882a593Smuzhiyun #endif
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /* COMPHY registers */
22*4882a593Smuzhiyun #define COMMON_PHY_CFG1_REG 0x0
23*4882a593Smuzhiyun #define COMMON_PHY_CFG1_PWR_UP_OFFSET 1
24*4882a593Smuzhiyun #define COMMON_PHY_CFG1_PWR_UP_MASK \
25*4882a593Smuzhiyun (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET)
26*4882a593Smuzhiyun #define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET 2
27*4882a593Smuzhiyun #define COMMON_PHY_CFG1_PIPE_SELECT_MASK \
28*4882a593Smuzhiyun (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET)
29*4882a593Smuzhiyun #define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET 13
30*4882a593Smuzhiyun #define COMMON_PHY_CFG1_PWR_ON_RESET_MASK \
31*4882a593Smuzhiyun (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET)
32*4882a593Smuzhiyun #define COMMON_PHY_CFG1_CORE_RSTN_OFFSET 14
33*4882a593Smuzhiyun #define COMMON_PHY_CFG1_CORE_RSTN_MASK \
34*4882a593Smuzhiyun (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET)
35*4882a593Smuzhiyun #define COMMON_PHY_PHY_MODE_OFFSET 15
36*4882a593Smuzhiyun #define COMMON_PHY_PHY_MODE_MASK \
37*4882a593Smuzhiyun (0x1 << COMMON_PHY_PHY_MODE_OFFSET)
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define COMMON_PHY_CFG6_REG 0x14
40*4882a593Smuzhiyun #define COMMON_PHY_CFG6_IF_40_SEL_OFFSET 18
41*4882a593Smuzhiyun #define COMMON_PHY_CFG6_IF_40_SEL_MASK \
42*4882a593Smuzhiyun (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET)
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define COMMON_SELECTOR_PHY_OFFSET 0x140
45*4882a593Smuzhiyun #define COMMON_SELECTOR_PIPE_OFFSET 0x144
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define COMMON_PHY_SD_CTRL1 0x148
48*4882a593Smuzhiyun #define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET 0
49*4882a593Smuzhiyun #define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK 0xFFFF
50*4882a593Smuzhiyun #define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24
51*4882a593Smuzhiyun #define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK \
52*4882a593Smuzhiyun (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
53*4882a593Smuzhiyun #define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25
54*4882a593Smuzhiyun #define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK \
55*4882a593Smuzhiyun (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
56*4882a593Smuzhiyun #define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26
57*4882a593Smuzhiyun #define COMMON_PHY_SD_CTRL1_RXAUI1_MASK \
58*4882a593Smuzhiyun (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET)
59*4882a593Smuzhiyun #define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27
60*4882a593Smuzhiyun #define COMMON_PHY_SD_CTRL1_RXAUI0_MASK \
61*4882a593Smuzhiyun (0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET)
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* ToDo: Get this address via DT */
64*4882a593Smuzhiyun #define MVEBU_CP0_REGS_BASE 0xF2000000UL
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun #define DFX_DEV_GEN_CTRL12 (MVEBU_CP0_REGS_BASE + 0x400280)
67*4882a593Smuzhiyun #define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET 7
68*4882a593Smuzhiyun #define DFX_DEV_GEN_PCIE_CLK_SRC_MASK \
69*4882a593Smuzhiyun (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET)
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun #define MAX_LANE_OPTIONS 10
72*4882a593Smuzhiyun #define MAX_UTMI_PHY_COUNT 3
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun struct comphy_mux_options {
75*4882a593Smuzhiyun u32 type;
76*4882a593Smuzhiyun u32 mux_value;
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun struct comphy_mux_data {
80*4882a593Smuzhiyun u32 max_lane_values;
81*4882a593Smuzhiyun struct comphy_mux_options mux_values[MAX_LANE_OPTIONS];
82*4882a593Smuzhiyun };
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun struct comphy_map {
85*4882a593Smuzhiyun u32 type;
86*4882a593Smuzhiyun u32 speed;
87*4882a593Smuzhiyun u32 invert;
88*4882a593Smuzhiyun bool clk_src;
89*4882a593Smuzhiyun bool end_point;
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun struct chip_serdes_phy_config {
93*4882a593Smuzhiyun struct comphy_mux_data *mux_data;
94*4882a593Smuzhiyun int (*ptr_comphy_chip_init)(struct chip_serdes_phy_config *,
95*4882a593Smuzhiyun struct comphy_map *);
96*4882a593Smuzhiyun void __iomem *comphy_base_addr;
97*4882a593Smuzhiyun void __iomem *hpipe3_base_addr;
98*4882a593Smuzhiyun u32 comphy_lanes_count;
99*4882a593Smuzhiyun u32 comphy_mux_bitcount;
100*4882a593Smuzhiyun u32 cp_index;
101*4882a593Smuzhiyun };
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /* Register helper functions */
104*4882a593Smuzhiyun void reg_set(void __iomem *addr, u32 data, u32 mask);
105*4882a593Smuzhiyun void reg_set_silent(void __iomem *addr, u32 data, u32 mask);
106*4882a593Smuzhiyun void reg_set16(void __iomem *addr, u16 data, u16 mask);
107*4882a593Smuzhiyun void reg_set_silent16(void __iomem *addr, u16 data, u16 mask);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* SoC specific init functions */
110*4882a593Smuzhiyun #ifdef CONFIG_ARMADA_3700
111*4882a593Smuzhiyun int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
112*4882a593Smuzhiyun struct comphy_map *serdes_map);
113*4882a593Smuzhiyun #else
comphy_a3700_init(struct chip_serdes_phy_config * ptr_chip_cfg,struct comphy_map * serdes_map)114*4882a593Smuzhiyun static inline int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
115*4882a593Smuzhiyun struct comphy_map *serdes_map)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun /*
118*4882a593Smuzhiyun * This function should never be called in this configuration, so
119*4882a593Smuzhiyun * lets return an error here.
120*4882a593Smuzhiyun */
121*4882a593Smuzhiyun return -1;
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun #endif
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun #ifdef CONFIG_ARMADA_8K
126*4882a593Smuzhiyun int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
127*4882a593Smuzhiyun struct comphy_map *serdes_map);
128*4882a593Smuzhiyun #else
comphy_cp110_init(struct chip_serdes_phy_config * ptr_chip_cfg,struct comphy_map * serdes_map)129*4882a593Smuzhiyun static inline int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
130*4882a593Smuzhiyun struct comphy_map *serdes_map)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun /*
133*4882a593Smuzhiyun * This function should never be called in this configuration, so
134*4882a593Smuzhiyun * lets return an error here.
135*4882a593Smuzhiyun */
136*4882a593Smuzhiyun return -1;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun #endif
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun void comphy_dedicated_phys_init(void);
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun /* MUX function */
143*4882a593Smuzhiyun void comphy_mux_init(struct chip_serdes_phy_config *ptr_chip_cfg,
144*4882a593Smuzhiyun struct comphy_map *comphy_map_data,
145*4882a593Smuzhiyun void __iomem *selector_base);
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun void comphy_pcie_config_set(u32 comphy_max_count,
148*4882a593Smuzhiyun struct comphy_map *serdes_map);
149*4882a593Smuzhiyun void comphy_pcie_config_detect(u32 comphy_max_count,
150*4882a593Smuzhiyun struct comphy_map *serdes_map);
151*4882a593Smuzhiyun void comphy_pcie_unit_general_config(u32 pex_index);
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun #endif /* _COMPHY_H_ */
154*4882a593Smuzhiyun
155