1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * SH7780 PCI Controller (PCIC) for U-Boot.
3*4882a593Smuzhiyun * (C) Dustin McIntire (dustin@sensoria.com)
4*4882a593Smuzhiyun * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5*4882a593Smuzhiyun * (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <pci.h>
13*4882a593Smuzhiyun #include <asm/processor.h>
14*4882a593Smuzhiyun #include <asm/pci.h>
15*4882a593Smuzhiyun #include <asm/io.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define SH7780_VENDOR_ID 0x1912
18*4882a593Smuzhiyun #define SH7780_DEVICE_ID 0x0002
19*4882a593Smuzhiyun #define SH7780_PCICR_PREFIX 0xA5000000
20*4882a593Smuzhiyun #define SH7780_PCICR_PFCS 0x00000800
21*4882a593Smuzhiyun #define SH7780_PCICR_FTO 0x00000400
22*4882a593Smuzhiyun #define SH7780_PCICR_PFE 0x00000200
23*4882a593Smuzhiyun #define SH7780_PCICR_TBS 0x00000100
24*4882a593Smuzhiyun #define SH7780_PCICR_ARBM 0x00000040
25*4882a593Smuzhiyun #define SH7780_PCICR_IOCS 0x00000004
26*4882a593Smuzhiyun #define SH7780_PCICR_PRST 0x00000002
27*4882a593Smuzhiyun #define SH7780_PCICR_CFIN 0x00000001
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define p4_in(addr) (*(vu_long *)addr)
30*4882a593Smuzhiyun #define p4_out(data, addr) (*(vu_long *)addr) = (data)
31*4882a593Smuzhiyun #define p4_inw(addr) (*(vu_short *)addr)
32*4882a593Smuzhiyun #define p4_outw(data, addr) (*(vu_short *)addr) = (data)
33*4882a593Smuzhiyun
pci_sh4_read_config_dword(struct pci_controller * hose,pci_dev_t dev,int offset,u32 * value)34*4882a593Smuzhiyun int pci_sh4_read_config_dword(struct pci_controller *hose,
35*4882a593Smuzhiyun pci_dev_t dev, int offset, u32 *value)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun u32 par_data = 0x80000000 | dev;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR);
40*4882a593Smuzhiyun *value = p4_in(SH7780_PCIPDR);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun return 0;
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
pci_sh4_write_config_dword(struct pci_controller * hose,pci_dev_t dev,int offset,u32 value)45*4882a593Smuzhiyun int pci_sh4_write_config_dword(struct pci_controller *hose,
46*4882a593Smuzhiyun pci_dev_t dev, int offset, u32 value)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun u32 par_data = 0x80000000 | dev;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR);
51*4882a593Smuzhiyun p4_out(value, SH7780_PCIPDR);
52*4882a593Smuzhiyun return 0;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
pci_sh7780_init(struct pci_controller * hose)55*4882a593Smuzhiyun int pci_sh7780_init(struct pci_controller *hose)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun p4_out(0x01, SH7780_PCIECR);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun if (p4_inw(SH7780_PCIVID) != SH7780_VENDOR_ID
60*4882a593Smuzhiyun && p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID) {
61*4882a593Smuzhiyun printf("PCI: Unknown PCI host bridge.\n");
62*4882a593Smuzhiyun return -1;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun printf("PCI: SH7780 PCI host bridge found.\n");
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* Toggle PCI reset pin */
67*4882a593Smuzhiyun p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_PRST), SH7780_PCICR);
68*4882a593Smuzhiyun udelay(100000);
69*4882a593Smuzhiyun p4_out(SH7780_PCICR_PREFIX, SH7780_PCICR);
70*4882a593Smuzhiyun p4_outw(0x0047, SH7780_PCICMD);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun p4_out(CONFIG_SH7780_PCI_LSR, SH7780_PCILSR0);
73*4882a593Smuzhiyun p4_out(CONFIG_SH7780_PCI_LAR, SH7780_PCILAR0);
74*4882a593Smuzhiyun p4_out(0x00000000, SH7780_PCILSR1);
75*4882a593Smuzhiyun p4_out(0, SH7780_PCILAR1);
76*4882a593Smuzhiyun p4_out(CONFIG_SH7780_PCI_BAR, SH7780_PCIMBAR0);
77*4882a593Smuzhiyun p4_out(0x00000000, SH7780_PCIMBAR1);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun p4_out(0xFD000000, SH7780_PCIMBR0);
80*4882a593Smuzhiyun p4_out(0x00FC0000, SH7780_PCIMBMR0);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* if use Operand Cache then enable PCICSCR Soonp bits. */
83*4882a593Smuzhiyun p4_out(0x08000000, SH7780_PCICSAR0);
84*4882a593Smuzhiyun p4_out(0x0000001B, SH7780_PCICSCR0); /* Snoop bit :On */
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_CFIN | SH7780_PCICR_ARBM
87*4882a593Smuzhiyun | SH7780_PCICR_FTO | SH7780_PCICR_PFCS | SH7780_PCICR_PFE),
88*4882a593Smuzhiyun SH7780_PCICR);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun pci_sh4_init(hose);
91*4882a593Smuzhiyun return 0;
92*4882a593Smuzhiyun }
93