1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * SH4 PCI Controller (PCIC) for U-Boot.
3*4882a593Smuzhiyun * (C) Dustin McIntire (dustin@sensoria.com)
4*4882a593Smuzhiyun * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5*4882a593Smuzhiyun * (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * u-boot/arch/sh/cpu/sh4/pci-sh4.c
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <asm/processor.h>
15*4882a593Smuzhiyun #include <asm/io.h>
16*4882a593Smuzhiyun #include <asm/pci.h>
17*4882a593Smuzhiyun #include <pci.h>
18*4882a593Smuzhiyun
pci_sh4_init(struct pci_controller * hose)19*4882a593Smuzhiyun int pci_sh4_init(struct pci_controller *hose)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun hose->first_busno = 0;
22*4882a593Smuzhiyun hose->region_count = 0;
23*4882a593Smuzhiyun hose->last_busno = 0xff;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* PCI memory space */
26*4882a593Smuzhiyun pci_set_region(hose->regions + 0,
27*4882a593Smuzhiyun CONFIG_PCI_MEM_BUS,
28*4882a593Smuzhiyun CONFIG_PCI_MEM_PHYS,
29*4882a593Smuzhiyun CONFIG_PCI_MEM_SIZE,
30*4882a593Smuzhiyun PCI_REGION_MEM);
31*4882a593Smuzhiyun hose->region_count++;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* PCI IO space */
34*4882a593Smuzhiyun pci_set_region(hose->regions + 1,
35*4882a593Smuzhiyun CONFIG_PCI_IO_BUS,
36*4882a593Smuzhiyun CONFIG_PCI_IO_PHYS,
37*4882a593Smuzhiyun CONFIG_PCI_IO_SIZE,
38*4882a593Smuzhiyun PCI_REGION_IO);
39*4882a593Smuzhiyun hose->region_count++;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #if defined(CONFIG_PCI_SYS_BUS)
42*4882a593Smuzhiyun /* PCI System Memory space */
43*4882a593Smuzhiyun pci_set_region(hose->regions + 2,
44*4882a593Smuzhiyun CONFIG_PCI_SYS_BUS,
45*4882a593Smuzhiyun CONFIG_PCI_SYS_PHYS,
46*4882a593Smuzhiyun CONFIG_PCI_SYS_SIZE,
47*4882a593Smuzhiyun PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
48*4882a593Smuzhiyun hose->region_count++;
49*4882a593Smuzhiyun #endif
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun udelay(1000);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun pci_set_ops(hose,
54*4882a593Smuzhiyun pci_hose_read_config_byte_via_dword,
55*4882a593Smuzhiyun pci_hose_read_config_word_via_dword,
56*4882a593Smuzhiyun pci_sh4_read_config_dword,
57*4882a593Smuzhiyun pci_hose_write_config_byte_via_dword,
58*4882a593Smuzhiyun pci_hose_write_config_word_via_dword,
59*4882a593Smuzhiyun pci_sh4_write_config_dword);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun pci_register_hose(hose);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun udelay(1000);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun #ifdef CONFIG_PCI_SCAN_SHOW
66*4882a593Smuzhiyun printf("PCI: Bus Dev VenId DevId Class Int\n");
67*4882a593Smuzhiyun #endif
68*4882a593Smuzhiyun hose->last_busno = pci_hose_scan(hose);
69*4882a593Smuzhiyun return 0;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
pci_skip_dev(struct pci_controller * hose,pci_dev_t dev)72*4882a593Smuzhiyun int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun return 0;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun #ifdef CONFIG_PCI_SCAN_SHOW
pci_print_dev(struct pci_controller * hose,pci_dev_t dev)78*4882a593Smuzhiyun int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun return 1;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun #endif /* CONFIG_PCI_SCAN_SHOW */
83