1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2013 Imagination Technologies
3*4882a593Smuzhiyun * Author: Paul Burton <paul.burton@imgtec.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <msc01.h>
10*4882a593Smuzhiyun #include <pci.h>
11*4882a593Smuzhiyun #include <pci_msc01.h>
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define PCI_ACCESS_READ 0
15*4882a593Smuzhiyun #define PCI_ACCESS_WRITE 1
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun struct msc01_pci_controller {
18*4882a593Smuzhiyun struct pci_controller hose;
19*4882a593Smuzhiyun void *base;
20*4882a593Smuzhiyun };
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun static inline struct msc01_pci_controller *
hose_to_msc01(struct pci_controller * hose)23*4882a593Smuzhiyun hose_to_msc01(struct pci_controller *hose)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun return container_of(hose, struct msc01_pci_controller, hose);
26*4882a593Smuzhiyun }
27*4882a593Smuzhiyun
msc01_config_access(struct msc01_pci_controller * msc01,unsigned char access_type,pci_dev_t bdf,int where,u32 * data)28*4882a593Smuzhiyun static int msc01_config_access(struct msc01_pci_controller *msc01,
29*4882a593Smuzhiyun unsigned char access_type, pci_dev_t bdf,
30*4882a593Smuzhiyun int where, u32 *data)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun const u32 aborts = MSC01_PCI_INTSTAT_MA_MSK | MSC01_PCI_INTSTAT_TA_MSK;
33*4882a593Smuzhiyun void *intstat = msc01->base + MSC01_PCI_INTSTAT_OFS;
34*4882a593Smuzhiyun void *cfgdata = msc01->base + MSC01_PCI_CFGDATA_OFS;
35*4882a593Smuzhiyun unsigned int bus = PCI_BUS(bdf);
36*4882a593Smuzhiyun unsigned int dev = PCI_DEV(bdf);
37*4882a593Smuzhiyun unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* clear abort status */
40*4882a593Smuzhiyun __raw_writel(aborts, intstat);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /* setup address */
43*4882a593Smuzhiyun __raw_writel((bus << MSC01_PCI_CFGADDR_BNUM_SHF) |
44*4882a593Smuzhiyun (dev << MSC01_PCI_CFGADDR_DNUM_SHF) |
45*4882a593Smuzhiyun (devfn << MSC01_PCI_CFGADDR_FNUM_SHF) |
46*4882a593Smuzhiyun ((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF),
47*4882a593Smuzhiyun msc01->base + MSC01_PCI_CFGADDR_OFS);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* perform access */
50*4882a593Smuzhiyun if (access_type == PCI_ACCESS_WRITE)
51*4882a593Smuzhiyun __raw_writel(*data, cfgdata);
52*4882a593Smuzhiyun else
53*4882a593Smuzhiyun *data = __raw_readl(cfgdata);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* check for aborts */
56*4882a593Smuzhiyun if (__raw_readl(intstat) & aborts) {
57*4882a593Smuzhiyun /* clear abort status */
58*4882a593Smuzhiyun __raw_writel(aborts, intstat);
59*4882a593Smuzhiyun return -1;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun return 0;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
msc01_read_config_dword(struct pci_controller * hose,pci_dev_t dev,int where,u32 * value)65*4882a593Smuzhiyun static int msc01_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
66*4882a593Smuzhiyun int where, u32 *value)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun struct msc01_pci_controller *msc01 = hose_to_msc01(hose);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun *value = 0xffffffff;
71*4882a593Smuzhiyun return msc01_config_access(msc01, PCI_ACCESS_READ, dev, where, value);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
msc01_write_config_dword(struct pci_controller * hose,pci_dev_t dev,int where,u32 value)74*4882a593Smuzhiyun static int msc01_write_config_dword(struct pci_controller *hose, pci_dev_t dev,
75*4882a593Smuzhiyun int where, u32 value)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun struct msc01_pci_controller *gt = hose_to_msc01(hose);
78*4882a593Smuzhiyun u32 data = value;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun return msc01_config_access(gt, PCI_ACCESS_WRITE, dev, where, &data);
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
msc01_pci_init(void * base,unsigned long sys_bus,unsigned long sys_phys,unsigned long sys_size,unsigned long mem_bus,unsigned long mem_phys,unsigned long mem_size,unsigned long io_bus,unsigned long io_phys,unsigned long io_size)83*4882a593Smuzhiyun void msc01_pci_init(void *base, unsigned long sys_bus, unsigned long sys_phys,
84*4882a593Smuzhiyun unsigned long sys_size, unsigned long mem_bus,
85*4882a593Smuzhiyun unsigned long mem_phys, unsigned long mem_size,
86*4882a593Smuzhiyun unsigned long io_bus, unsigned long io_phys,
87*4882a593Smuzhiyun unsigned long io_size)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun static struct msc01_pci_controller global_msc01;
90*4882a593Smuzhiyun struct msc01_pci_controller *msc01;
91*4882a593Smuzhiyun struct pci_controller *hose;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun msc01 = &global_msc01;
94*4882a593Smuzhiyun msc01->base = base;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun hose = &msc01->hose;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun hose->first_busno = 0;
99*4882a593Smuzhiyun hose->last_busno = 0;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun /* System memory space */
102*4882a593Smuzhiyun pci_set_region(&hose->regions[0], sys_bus, sys_phys, sys_size,
103*4882a593Smuzhiyun PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /* PCI memory space */
106*4882a593Smuzhiyun pci_set_region(&hose->regions[1], mem_bus, mem_phys, mem_size,
107*4882a593Smuzhiyun PCI_REGION_MEM);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* PCI I/O space */
110*4882a593Smuzhiyun pci_set_region(&hose->regions[2], io_bus, io_phys, io_size,
111*4882a593Smuzhiyun PCI_REGION_IO);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun hose->region_count = 3;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun pci_set_ops(hose,
116*4882a593Smuzhiyun pci_hose_read_config_byte_via_dword,
117*4882a593Smuzhiyun pci_hose_read_config_word_via_dword,
118*4882a593Smuzhiyun msc01_read_config_dword,
119*4882a593Smuzhiyun pci_hose_write_config_byte_via_dword,
120*4882a593Smuzhiyun pci_hose_write_config_word_via_dword,
121*4882a593Smuzhiyun msc01_write_config_dword);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun pci_register_hose(hose);
124*4882a593Smuzhiyun hose->last_busno = pci_hose_scan(hose);
125*4882a593Smuzhiyun }
126