1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2014 Google, Inc
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
5*4882a593Smuzhiyun * Andreas Heppel <aheppel@sysgo.de>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * (C) Copyright 2002, 2003
8*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <common.h>
14*4882a593Smuzhiyun #include <dm.h>
15*4882a593Smuzhiyun #include <errno.h>
16*4882a593Smuzhiyun #include <pci.h>
17*4882a593Smuzhiyun #include <asm/io.h>
18*4882a593Smuzhiyun
pci_class_str(u8 class)19*4882a593Smuzhiyun const char *pci_class_str(u8 class)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun switch (class) {
22*4882a593Smuzhiyun case PCI_CLASS_NOT_DEFINED:
23*4882a593Smuzhiyun return "Build before PCI Rev2.0";
24*4882a593Smuzhiyun break;
25*4882a593Smuzhiyun case PCI_BASE_CLASS_STORAGE:
26*4882a593Smuzhiyun return "Mass storage controller";
27*4882a593Smuzhiyun break;
28*4882a593Smuzhiyun case PCI_BASE_CLASS_NETWORK:
29*4882a593Smuzhiyun return "Network controller";
30*4882a593Smuzhiyun break;
31*4882a593Smuzhiyun case PCI_BASE_CLASS_DISPLAY:
32*4882a593Smuzhiyun return "Display controller";
33*4882a593Smuzhiyun break;
34*4882a593Smuzhiyun case PCI_BASE_CLASS_MULTIMEDIA:
35*4882a593Smuzhiyun return "Multimedia device";
36*4882a593Smuzhiyun break;
37*4882a593Smuzhiyun case PCI_BASE_CLASS_MEMORY:
38*4882a593Smuzhiyun return "Memory controller";
39*4882a593Smuzhiyun break;
40*4882a593Smuzhiyun case PCI_BASE_CLASS_BRIDGE:
41*4882a593Smuzhiyun return "Bridge device";
42*4882a593Smuzhiyun break;
43*4882a593Smuzhiyun case PCI_BASE_CLASS_COMMUNICATION:
44*4882a593Smuzhiyun return "Simple comm. controller";
45*4882a593Smuzhiyun break;
46*4882a593Smuzhiyun case PCI_BASE_CLASS_SYSTEM:
47*4882a593Smuzhiyun return "Base system peripheral";
48*4882a593Smuzhiyun break;
49*4882a593Smuzhiyun case PCI_BASE_CLASS_INPUT:
50*4882a593Smuzhiyun return "Input device";
51*4882a593Smuzhiyun break;
52*4882a593Smuzhiyun case PCI_BASE_CLASS_DOCKING:
53*4882a593Smuzhiyun return "Docking station";
54*4882a593Smuzhiyun break;
55*4882a593Smuzhiyun case PCI_BASE_CLASS_PROCESSOR:
56*4882a593Smuzhiyun return "Processor";
57*4882a593Smuzhiyun break;
58*4882a593Smuzhiyun case PCI_BASE_CLASS_SERIAL:
59*4882a593Smuzhiyun return "Serial bus controller";
60*4882a593Smuzhiyun break;
61*4882a593Smuzhiyun case PCI_BASE_CLASS_INTELLIGENT:
62*4882a593Smuzhiyun return "Intelligent controller";
63*4882a593Smuzhiyun break;
64*4882a593Smuzhiyun case PCI_BASE_CLASS_SATELLITE:
65*4882a593Smuzhiyun return "Satellite controller";
66*4882a593Smuzhiyun break;
67*4882a593Smuzhiyun case PCI_BASE_CLASS_CRYPT:
68*4882a593Smuzhiyun return "Cryptographic device";
69*4882a593Smuzhiyun break;
70*4882a593Smuzhiyun case PCI_BASE_CLASS_SIGNAL_PROCESSING:
71*4882a593Smuzhiyun return "DSP";
72*4882a593Smuzhiyun break;
73*4882a593Smuzhiyun case PCI_CLASS_OTHERS:
74*4882a593Smuzhiyun return "Does not fit any class";
75*4882a593Smuzhiyun break;
76*4882a593Smuzhiyun default:
77*4882a593Smuzhiyun return "???";
78*4882a593Smuzhiyun break;
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
pci_skip_dev(struct pci_controller * hose,pci_dev_t dev)82*4882a593Smuzhiyun __weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun /*
85*4882a593Smuzhiyun * Check if pci device should be skipped in configuration
86*4882a593Smuzhiyun */
87*4882a593Smuzhiyun if (dev == PCI_BDF(hose->first_busno, 0, 0)) {
88*4882a593Smuzhiyun #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
89*4882a593Smuzhiyun /*
90*4882a593Smuzhiyun * Only skip configuration if "pciconfighost" is not set
91*4882a593Smuzhiyun */
92*4882a593Smuzhiyun if (env_get("pciconfighost") == NULL)
93*4882a593Smuzhiyun return 1;
94*4882a593Smuzhiyun #else
95*4882a593Smuzhiyun return 1;
96*4882a593Smuzhiyun #endif
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun return 0;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
103*4882a593Smuzhiyun /* Get a virtual address associated with a BAR region */
pci_map_bar(pci_dev_t pdev,int bar,int flags)104*4882a593Smuzhiyun void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun pci_addr_t pci_bus_addr;
107*4882a593Smuzhiyun u32 bar_response;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* read BAR address */
110*4882a593Smuzhiyun pci_read_config_dword(pdev, bar, &bar_response);
111*4882a593Smuzhiyun pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /*
114*4882a593Smuzhiyun * Pass "0" as the length argument to pci_bus_to_virt. The arg
115*4882a593Smuzhiyun * isn't actualy used on any platform because u-boot assumes a static
116*4882a593Smuzhiyun * linear mapping. In the future, this could read the BAR size
117*4882a593Smuzhiyun * and pass that as the size if needed.
118*4882a593Smuzhiyun */
119*4882a593Smuzhiyun return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE);
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
pci_write_bar32(struct pci_controller * hose,pci_dev_t dev,int barnum,u32 addr_and_ctrl)122*4882a593Smuzhiyun void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
123*4882a593Smuzhiyun u32 addr_and_ctrl)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun int bar;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun bar = PCI_BASE_ADDRESS_0 + barnum * 4;
128*4882a593Smuzhiyun pci_hose_write_config_dword(hose, dev, bar, addr_and_ctrl);
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
pci_read_bar32(struct pci_controller * hose,pci_dev_t dev,int barnum)131*4882a593Smuzhiyun u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun u32 addr;
134*4882a593Smuzhiyun int bar;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun bar = PCI_BASE_ADDRESS_0 + barnum * 4;
137*4882a593Smuzhiyun pci_hose_read_config_dword(hose, dev, bar, &addr);
138*4882a593Smuzhiyun if (addr & PCI_BASE_ADDRESS_SPACE_IO)
139*4882a593Smuzhiyun return addr & PCI_BASE_ADDRESS_IO_MASK;
140*4882a593Smuzhiyun else
141*4882a593Smuzhiyun return addr & PCI_BASE_ADDRESS_MEM_MASK;
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
__pci_hose_bus_to_phys(struct pci_controller * hose,pci_addr_t bus_addr,unsigned long flags,unsigned long skip_mask,phys_addr_t * pa)144*4882a593Smuzhiyun int __pci_hose_bus_to_phys(struct pci_controller *hose,
145*4882a593Smuzhiyun pci_addr_t bus_addr,
146*4882a593Smuzhiyun unsigned long flags,
147*4882a593Smuzhiyun unsigned long skip_mask,
148*4882a593Smuzhiyun phys_addr_t *pa)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun struct pci_region *res;
151*4882a593Smuzhiyun int i;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun for (i = 0; i < hose->region_count; i++) {
154*4882a593Smuzhiyun res = &hose->regions[i];
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
157*4882a593Smuzhiyun continue;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun if (res->flags & skip_mask)
160*4882a593Smuzhiyun continue;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun if (bus_addr >= res->bus_start &&
163*4882a593Smuzhiyun (bus_addr - res->bus_start) < res->size) {
164*4882a593Smuzhiyun *pa = (bus_addr - res->bus_start + res->phys_start);
165*4882a593Smuzhiyun return 0;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun return 1;
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun
pci_hose_bus_to_phys(struct pci_controller * hose,pci_addr_t bus_addr,unsigned long flags)172*4882a593Smuzhiyun phys_addr_t pci_hose_bus_to_phys(struct pci_controller *hose,
173*4882a593Smuzhiyun pci_addr_t bus_addr,
174*4882a593Smuzhiyun unsigned long flags)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun phys_addr_t phys_addr = 0;
177*4882a593Smuzhiyun int ret;
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun if (!hose) {
180*4882a593Smuzhiyun puts("pci_hose_bus_to_phys: invalid hose\n");
181*4882a593Smuzhiyun return phys_addr;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun /*
185*4882a593Smuzhiyun * if PCI_REGION_MEM is set we do a two pass search with preference
186*4882a593Smuzhiyun * on matches that don't have PCI_REGION_SYS_MEMORY set
187*4882a593Smuzhiyun */
188*4882a593Smuzhiyun if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
189*4882a593Smuzhiyun ret = __pci_hose_bus_to_phys(hose, bus_addr,
190*4882a593Smuzhiyun flags, PCI_REGION_SYS_MEMORY, &phys_addr);
191*4882a593Smuzhiyun if (!ret)
192*4882a593Smuzhiyun return phys_addr;
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr);
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun if (ret)
198*4882a593Smuzhiyun puts("pci_hose_bus_to_phys: invalid physical address\n");
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun return phys_addr;
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
__pci_hose_phys_to_bus(struct pci_controller * hose,phys_addr_t phys_addr,unsigned long flags,unsigned long skip_mask,pci_addr_t * ba)203*4882a593Smuzhiyun int __pci_hose_phys_to_bus(struct pci_controller *hose,
204*4882a593Smuzhiyun phys_addr_t phys_addr,
205*4882a593Smuzhiyun unsigned long flags,
206*4882a593Smuzhiyun unsigned long skip_mask,
207*4882a593Smuzhiyun pci_addr_t *ba)
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun struct pci_region *res;
210*4882a593Smuzhiyun pci_addr_t bus_addr;
211*4882a593Smuzhiyun int i;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun for (i = 0; i < hose->region_count; i++) {
214*4882a593Smuzhiyun res = &hose->regions[i];
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
217*4882a593Smuzhiyun continue;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun if (res->flags & skip_mask)
220*4882a593Smuzhiyun continue;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun bus_addr = phys_addr - res->phys_start + res->bus_start;
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun if (bus_addr >= res->bus_start &&
225*4882a593Smuzhiyun (bus_addr - res->bus_start) < res->size) {
226*4882a593Smuzhiyun *ba = bus_addr;
227*4882a593Smuzhiyun return 0;
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun return 1;
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun /*
235*4882a593Smuzhiyun * pci_hose_phys_to_bus(): Convert physical address to bus address
236*4882a593Smuzhiyun * @hose: PCI hose of the root PCI controller
237*4882a593Smuzhiyun * @phys_addr: physical address to convert
238*4882a593Smuzhiyun * @flags: flags of pci regions
239*4882a593Smuzhiyun * @return bus address if OK, 0 on error
240*4882a593Smuzhiyun */
pci_hose_phys_to_bus(struct pci_controller * hose,phys_addr_t phys_addr,unsigned long flags)241*4882a593Smuzhiyun pci_addr_t pci_hose_phys_to_bus(struct pci_controller *hose,
242*4882a593Smuzhiyun phys_addr_t phys_addr,
243*4882a593Smuzhiyun unsigned long flags)
244*4882a593Smuzhiyun {
245*4882a593Smuzhiyun pci_addr_t bus_addr = 0;
246*4882a593Smuzhiyun int ret;
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun if (!hose) {
249*4882a593Smuzhiyun puts("pci_hose_phys_to_bus: invalid hose\n");
250*4882a593Smuzhiyun return bus_addr;
251*4882a593Smuzhiyun }
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun /*
254*4882a593Smuzhiyun * if PCI_REGION_MEM is set we do a two pass search with preference
255*4882a593Smuzhiyun * on matches that don't have PCI_REGION_SYS_MEMORY set
256*4882a593Smuzhiyun */
257*4882a593Smuzhiyun if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
258*4882a593Smuzhiyun ret = __pci_hose_phys_to_bus(hose, phys_addr,
259*4882a593Smuzhiyun flags, PCI_REGION_SYS_MEMORY, &bus_addr);
260*4882a593Smuzhiyun if (!ret)
261*4882a593Smuzhiyun return bus_addr;
262*4882a593Smuzhiyun }
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr);
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun if (ret)
267*4882a593Smuzhiyun puts("pci_hose_phys_to_bus: invalid physical address\n");
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun return bus_addr;
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun
pci_find_device(unsigned int vendor,unsigned int device,int index)272*4882a593Smuzhiyun pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
273*4882a593Smuzhiyun {
274*4882a593Smuzhiyun struct pci_device_id ids[2] = { {}, {0, 0} };
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun ids[0].vendor = vendor;
277*4882a593Smuzhiyun ids[0].device = device;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun return pci_find_devices(ids, index);
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun
pci_hose_find_devices(struct pci_controller * hose,int busnum,struct pci_device_id * ids,int * indexp)282*4882a593Smuzhiyun pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
283*4882a593Smuzhiyun struct pci_device_id *ids, int *indexp)
284*4882a593Smuzhiyun {
285*4882a593Smuzhiyun int found_multi = 0;
286*4882a593Smuzhiyun u16 vendor, device;
287*4882a593Smuzhiyun u8 header_type;
288*4882a593Smuzhiyun pci_dev_t bdf;
289*4882a593Smuzhiyun int i;
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun for (bdf = PCI_BDF(busnum, 0, 0);
292*4882a593Smuzhiyun bdf < PCI_BDF(busnum + 1, 0, 0);
293*4882a593Smuzhiyun bdf += PCI_BDF(0, 0, 1)) {
294*4882a593Smuzhiyun if (pci_skip_dev(hose, bdf))
295*4882a593Smuzhiyun continue;
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun if (!PCI_FUNC(bdf)) {
298*4882a593Smuzhiyun pci_read_config_byte(bdf, PCI_HEADER_TYPE,
299*4882a593Smuzhiyun &header_type);
300*4882a593Smuzhiyun found_multi = header_type & 0x80;
301*4882a593Smuzhiyun } else {
302*4882a593Smuzhiyun if (!found_multi)
303*4882a593Smuzhiyun continue;
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun pci_read_config_word(bdf, PCI_VENDOR_ID, &vendor);
307*4882a593Smuzhiyun pci_read_config_word(bdf, PCI_DEVICE_ID, &device);
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun for (i = 0; ids[i].vendor != 0; i++) {
310*4882a593Smuzhiyun if (vendor == ids[i].vendor &&
311*4882a593Smuzhiyun device == ids[i].device) {
312*4882a593Smuzhiyun if ((*indexp) <= 0)
313*4882a593Smuzhiyun return bdf;
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun (*indexp)--;
316*4882a593Smuzhiyun }
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun return -1;
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun
pci_find_class(uint find_class,int index)323*4882a593Smuzhiyun pci_dev_t pci_find_class(uint find_class, int index)
324*4882a593Smuzhiyun {
325*4882a593Smuzhiyun int bus;
326*4882a593Smuzhiyun int devnum;
327*4882a593Smuzhiyun pci_dev_t bdf;
328*4882a593Smuzhiyun uint32_t class;
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun for (bus = 0; bus <= pci_last_busno(); bus++) {
331*4882a593Smuzhiyun for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES - 1; devnum++) {
332*4882a593Smuzhiyun pci_read_config_dword(PCI_BDF(bus, devnum, 0),
333*4882a593Smuzhiyun PCI_CLASS_REVISION, &class);
334*4882a593Smuzhiyun if (class >> 16 == 0xffff)
335*4882a593Smuzhiyun continue;
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun for (bdf = PCI_BDF(bus, devnum, 0);
338*4882a593Smuzhiyun bdf <= PCI_BDF(bus, devnum,
339*4882a593Smuzhiyun PCI_MAX_PCI_FUNCTIONS - 1);
340*4882a593Smuzhiyun bdf += PCI_BDF(0, 0, 1)) {
341*4882a593Smuzhiyun pci_read_config_dword(bdf, PCI_CLASS_REVISION,
342*4882a593Smuzhiyun &class);
343*4882a593Smuzhiyun class >>= 8;
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun if (class != find_class)
346*4882a593Smuzhiyun continue;
347*4882a593Smuzhiyun /*
348*4882a593Smuzhiyun * Decrement the index. We want to return the
349*4882a593Smuzhiyun * correct device, so index is 0 for the first
350*4882a593Smuzhiyun * matching device, 1 for the second, etc.
351*4882a593Smuzhiyun */
352*4882a593Smuzhiyun if (index) {
353*4882a593Smuzhiyun index--;
354*4882a593Smuzhiyun continue;
355*4882a593Smuzhiyun }
356*4882a593Smuzhiyun /* Return index'th controller. */
357*4882a593Smuzhiyun return bdf;
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun }
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun return -ENODEV;
363*4882a593Smuzhiyun }
364*4882a593Smuzhiyun #endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */
365