1*4882a593Smuzhiyunmenuconfig PCI 2*4882a593Smuzhiyun bool "PCI support" 3*4882a593Smuzhiyun default y if PPC 4*4882a593Smuzhiyun help 5*4882a593Smuzhiyun Enable support for PCI (Peripheral Interconnect Bus), a type of bus 6*4882a593Smuzhiyun used on some devices to allow the CPU to communicate with its 7*4882a593Smuzhiyun peripherals. 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunif PCI 10*4882a593Smuzhiyun 11*4882a593Smuzhiyunconfig DM_PCI 12*4882a593Smuzhiyun bool "Enable driver model for PCI" 13*4882a593Smuzhiyun depends on DM 14*4882a593Smuzhiyun help 15*4882a593Smuzhiyun Use driver model for PCI. Driver model is the new method for 16*4882a593Smuzhiyun orgnising devices in U-Boot. For PCI, driver model keeps track of 17*4882a593Smuzhiyun available PCI devices, allows scanning of PCI buses and provides 18*4882a593Smuzhiyun device configuration support. 19*4882a593Smuzhiyun 20*4882a593Smuzhiyunconfig DM_PCI_COMPAT 21*4882a593Smuzhiyun bool "Enable compatible functions for PCI" 22*4882a593Smuzhiyun depends on DM_PCI 23*4882a593Smuzhiyun help 24*4882a593Smuzhiyun Enable compatibility functions for PCI so that old code can be used 25*4882a593Smuzhiyun with CONFIG_DM_PCI enabled. This should be used as an interim 26*4882a593Smuzhiyun measure when porting a board to use driver model for PCI. Once the 27*4882a593Smuzhiyun board is fully supported, this option should be disabled. 28*4882a593Smuzhiyun 29*4882a593Smuzhiyunconfig PCI_PNP 30*4882a593Smuzhiyun bool "Enable Plug & Play support for PCI" 31*4882a593Smuzhiyun depends on PCI || DM_PCI 32*4882a593Smuzhiyun default y 33*4882a593Smuzhiyun help 34*4882a593Smuzhiyun Enable PCI memory and I/O space resource allocation and assignment. 35*4882a593Smuzhiyun 36*4882a593Smuzhiyunconfig PCIE_DW_MVEBU 37*4882a593Smuzhiyun bool "Enable Armada-8K PCIe driver (DesignWare core)" 38*4882a593Smuzhiyun default n 39*4882a593Smuzhiyun depends on DM_PCI 40*4882a593Smuzhiyun depends on ARMADA_8K 41*4882a593Smuzhiyun help 42*4882a593Smuzhiyun Say Y here if you want to enable PCIe controller support on 43*4882a593Smuzhiyun Armada-8K SoCs. The PCIe controller on Armada-8K is based on 44*4882a593Smuzhiyun DesignWare hardware. 45*4882a593Smuzhiyun 46*4882a593Smuzhiyunconfig PCI_SANDBOX 47*4882a593Smuzhiyun bool "Sandbox PCI support" 48*4882a593Smuzhiyun depends on SANDBOX && DM_PCI 49*4882a593Smuzhiyun help 50*4882a593Smuzhiyun Support PCI on sandbox, as an emulated bus. This permits testing of 51*4882a593Smuzhiyun PCI feature such as bus scanning, device configuration and device 52*4882a593Smuzhiyun access. The available (emulated) devices are defined statically in 53*4882a593Smuzhiyun the device tree but the normal PCI scan technique is used to find 54*4882a593Smuzhiyun then. 55*4882a593Smuzhiyun 56*4882a593Smuzhiyunconfig PCI_TEGRA 57*4882a593Smuzhiyun bool "Tegra PCI support" 58*4882a593Smuzhiyun depends on TEGRA 59*4882a593Smuzhiyun depends on (TEGRA186 && POWER_DOMAIN) || (!TEGRA186) 60*4882a593Smuzhiyun help 61*4882a593Smuzhiyun Enable support for the PCIe controller found on some generations of 62*4882a593Smuzhiyun Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 63*4882a593Smuzhiyun 3 root ports with a total of 6 lanes and Tegra124 has 2 root ports 64*4882a593Smuzhiyun with a total of 5 lanes. Some boards require this for Ethernet 65*4882a593Smuzhiyun support to work (e.g. beaver, jetson-tk1). 66*4882a593Smuzhiyun 67*4882a593Smuzhiyunconfig PCI_XILINX 68*4882a593Smuzhiyun bool "Xilinx AXI Bridge for PCI Express" 69*4882a593Smuzhiyun depends on DM_PCI 70*4882a593Smuzhiyun help 71*4882a593Smuzhiyun Enable support for the Xilinx AXI bridge for PCI express, an IP block 72*4882a593Smuzhiyun which can be used on some generations of Xilinx FPGAs. 73*4882a593Smuzhiyun 74*4882a593Smuzhiyunconfig PCIE_LAYERSCAPE 75*4882a593Smuzhiyun bool "Layerscape PCIe support" 76*4882a593Smuzhiyun depends on DM_PCI 77*4882a593Smuzhiyun help 78*4882a593Smuzhiyun Support Layerscape PCIe. The Layerscape SoC may have one or several 79*4882a593Smuzhiyun PCIe controllers. The PCIe may works in RC or EP mode according to 80*4882a593Smuzhiyun RCW[HOST_AGT_PEX] setting. 81*4882a593Smuzhiyun 82*4882a593Smuzhiyunconfig PCIE_DW_ROCKCHIP 83*4882a593Smuzhiyun bool "Rockchip DesignWare PCIe controller" 84*4882a593Smuzhiyun depends on DM_PCI 85*4882a593Smuzhiyun depends on ARCH_ROCKCHIP 86*4882a593Smuzhiyun select CONFIG_DM_REGULATOR_GPIO 87*4882a593Smuzhiyun help 88*4882a593Smuzhiyun Enables support for the DW PCIe controller in the Rockchip SoC. 89*4882a593Smuzhiyun 90*4882a593Smuzhiyunendif 91