1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2014 Google, Inc
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <dm.h>
9*4882a593Smuzhiyun #include <pch.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #define GPIO_BASE 0x48
12*4882a593Smuzhiyun #define IO_BASE 0x4c
13*4882a593Smuzhiyun #define SBASE_ADDR 0x54
14*4882a593Smuzhiyun
pch9_get_spi_base(struct udevice * dev,ulong * sbasep)15*4882a593Smuzhiyun static int pch9_get_spi_base(struct udevice *dev, ulong *sbasep)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun uint32_t sbase_addr;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun dm_pci_read_config32(dev, SBASE_ADDR, &sbase_addr);
20*4882a593Smuzhiyun *sbasep = sbase_addr & 0xfffffe00;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun return 0;
23*4882a593Smuzhiyun }
24*4882a593Smuzhiyun
pch9_get_gpio_base(struct udevice * dev,u32 * gbasep)25*4882a593Smuzhiyun static int pch9_get_gpio_base(struct udevice *dev, u32 *gbasep)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun u32 base;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /*
30*4882a593Smuzhiyun * GPIO_BASE moved to its current offset with ICH6, but prior to
31*4882a593Smuzhiyun * that it was unused (or undocumented). Check that it looks
32*4882a593Smuzhiyun * okay: not all ones or zeros.
33*4882a593Smuzhiyun *
34*4882a593Smuzhiyun * Note we don't need check bit0 here, because the Tunnel Creek
35*4882a593Smuzhiyun * GPIO base address register bit0 is reserved (read returns 0),
36*4882a593Smuzhiyun * while on the Ivybridge the bit0 is used to indicate it is an
37*4882a593Smuzhiyun * I/O space.
38*4882a593Smuzhiyun */
39*4882a593Smuzhiyun dm_pci_read_config32(dev, GPIO_BASE, &base);
40*4882a593Smuzhiyun if (base == 0x00000000 || base == 0xffffffff) {
41*4882a593Smuzhiyun debug("%s: unexpected BASE value\n", __func__);
42*4882a593Smuzhiyun return -ENODEV;
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /*
46*4882a593Smuzhiyun * Okay, I guess we're looking at the right device. The actual
47*4882a593Smuzhiyun * GPIO registers are in the PCI device's I/O space, starting
48*4882a593Smuzhiyun * at the offset that we just read. Bit 0 indicates that it's
49*4882a593Smuzhiyun * an I/O address, not a memory address, so mask that off.
50*4882a593Smuzhiyun */
51*4882a593Smuzhiyun *gbasep = base & 1 ? base & ~3 : base & ~15;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun return 0;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
pch9_get_io_base(struct udevice * dev,u32 * iobasep)56*4882a593Smuzhiyun static int pch9_get_io_base(struct udevice *dev, u32 *iobasep)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun u32 base;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun dm_pci_read_config32(dev, IO_BASE, &base);
61*4882a593Smuzhiyun if (base == 0x00000000 || base == 0xffffffff) {
62*4882a593Smuzhiyun debug("%s: unexpected BASE value\n", __func__);
63*4882a593Smuzhiyun return -ENODEV;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun *iobasep = base & 1 ? base & ~3 : base & ~15;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun return 0;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun static const struct pch_ops pch9_ops = {
72*4882a593Smuzhiyun .get_spi_base = pch9_get_spi_base,
73*4882a593Smuzhiyun .get_gpio_base = pch9_get_gpio_base,
74*4882a593Smuzhiyun .get_io_base = pch9_get_io_base,
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun static const struct udevice_id pch9_ids[] = {
78*4882a593Smuzhiyun { .compatible = "intel,pch9" },
79*4882a593Smuzhiyun { }
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun U_BOOT_DRIVER(pch9_drv) = {
83*4882a593Smuzhiyun .name = "intel-pch9",
84*4882a593Smuzhiyun .id = UCLASS_PCH,
85*4882a593Smuzhiyun .of_match = pch9_ids,
86*4882a593Smuzhiyun .ops = &pch9_ops,
87*4882a593Smuzhiyun };
88