1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2014 Google, Inc
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <dm.h>
9*4882a593Smuzhiyun #include <pch.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #define GPIO_BASE 0x44
12*4882a593Smuzhiyun #define BIOS_CTRL 0xd8
13*4882a593Smuzhiyun
pch7_get_spi_base(struct udevice * dev,ulong * sbasep)14*4882a593Smuzhiyun static int pch7_get_spi_base(struct udevice *dev, ulong *sbasep)
15*4882a593Smuzhiyun {
16*4882a593Smuzhiyun u32 rcba;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun dm_pci_read_config32(dev, PCH_RCBA, &rcba);
19*4882a593Smuzhiyun /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
20*4882a593Smuzhiyun rcba = rcba & 0xffffc000;
21*4882a593Smuzhiyun *sbasep = rcba + 0x3020;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun return 0;
24*4882a593Smuzhiyun }
25*4882a593Smuzhiyun
pch7_set_spi_protect(struct udevice * dev,bool protect)26*4882a593Smuzhiyun static int pch7_set_spi_protect(struct udevice *dev, bool protect)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun uint8_t bios_cntl;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* Adjust the BIOS write protect to dis/allow write commands */
31*4882a593Smuzhiyun dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl);
32*4882a593Smuzhiyun if (protect)
33*4882a593Smuzhiyun bios_cntl &= ~BIOS_CTRL_BIOSWE;
34*4882a593Smuzhiyun else
35*4882a593Smuzhiyun bios_cntl |= BIOS_CTRL_BIOSWE;
36*4882a593Smuzhiyun dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun return 0;
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
pch7_get_gpio_base(struct udevice * dev,u32 * gbasep)41*4882a593Smuzhiyun static int pch7_get_gpio_base(struct udevice *dev, u32 *gbasep)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun u32 base;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /*
46*4882a593Smuzhiyun * GPIO_BASE moved to its current offset with ICH6, but prior to
47*4882a593Smuzhiyun * that it was unused (or undocumented). Check that it looks
48*4882a593Smuzhiyun * okay: not all ones or zeros.
49*4882a593Smuzhiyun *
50*4882a593Smuzhiyun * Note we don't need check bit0 here, because the Tunnel Creek
51*4882a593Smuzhiyun * GPIO base address register bit0 is reserved (read returns 0),
52*4882a593Smuzhiyun * while on the Ivybridge the bit0 is used to indicate it is an
53*4882a593Smuzhiyun * I/O space.
54*4882a593Smuzhiyun */
55*4882a593Smuzhiyun dm_pci_read_config32(dev, GPIO_BASE, &base);
56*4882a593Smuzhiyun if (base == 0x00000000 || base == 0xffffffff) {
57*4882a593Smuzhiyun debug("%s: unexpected BASE value\n", __func__);
58*4882a593Smuzhiyun return -ENODEV;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /*
62*4882a593Smuzhiyun * Okay, I guess we're looking at the right device. The actual
63*4882a593Smuzhiyun * GPIO registers are in the PCI device's I/O space, starting
64*4882a593Smuzhiyun * at the offset that we just read. Bit 0 indicates that it's
65*4882a593Smuzhiyun * an I/O address, not a memory address, so mask that off.
66*4882a593Smuzhiyun */
67*4882a593Smuzhiyun *gbasep = base & 1 ? base & ~3 : base & ~15;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun return 0;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun static const struct pch_ops pch7_ops = {
73*4882a593Smuzhiyun .get_spi_base = pch7_get_spi_base,
74*4882a593Smuzhiyun .set_spi_protect = pch7_set_spi_protect,
75*4882a593Smuzhiyun .get_gpio_base = pch7_get_gpio_base,
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun static const struct udevice_id pch7_ids[] = {
79*4882a593Smuzhiyun { .compatible = "intel,pch7" },
80*4882a593Smuzhiyun { }
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun U_BOOT_DRIVER(pch7_drv) = {
84*4882a593Smuzhiyun .name = "intel-pch7",
85*4882a593Smuzhiyun .id = UCLASS_PCH,
86*4882a593Smuzhiyun .of_match = pch7_ids,
87*4882a593Smuzhiyun .ops = &pch7_ops,
88*4882a593Smuzhiyun };
89