1 /* 2 * Xilinx xps_ll_temac ethernet driver for u-boot 3 * 4 * FIFO sub-controller interface 5 * 6 * Copyright (C) 2011 - 2012 Stephan Linz <linz@li-pro.net> 7 * Copyright (C) 2008 - 2011 Michal Simek <monstr@monstr.eu> 8 * Copyright (C) 2008 - 2011 PetaLogix 9 * 10 * Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver 11 * Copyright (C) 2008 Nissin Systems Co.,Ltd. 12 * March 2008 created 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 * 16 * [0]: http://www.xilinx.com/support/documentation 17 * 18 * [S]: [0]/ip_documentation/xps_ll_temac.pdf 19 * [A]: [0]/application_notes/xapp1041.pdf 20 */ 21 #ifndef _XILINX_LL_TEMAC_FIFO_ 22 #define _XILINX_LL_TEMAC_FIFO_ 23 24 #include <net.h> 25 26 #include <asm/types.h> 27 #include <asm/byteorder.h> 28 29 #if !defined(__BIG_ENDIAN) 30 # error LL_TEMAC requires big endianess 31 #endif 32 33 /* 34 * FIFO Register Definition 35 * 36 * Used for memory mapped access from and to (Rd/Td) the LocalLink (LL) 37 * Tri-Mode Ether MAC (TEMAC) via the 2 kb full duplex FIFO Controller, 38 * one for each. 39 * 40 * [1]: [0]/ip_documentation/xps_ll_fifo.pdf 41 * page 10, Registers Definition 42 */ 43 struct fifo_ctrl { 44 u32 isr; /* Interrupt Status Register (RW) */ 45 u32 ier; /* Interrupt Enable Register (RW) */ 46 u32 tdfr; /* Transmit Data FIFO Reset (WO) */ 47 u32 tdfv; /* Transmit Data FIFO Vacancy (RO) */ 48 u32 tdfd; /* Transmit Data FIFO 32bit wide Data write port (WO) */ 49 u32 tlf; /* Transmit Length FIFO (WO) */ 50 u32 rdfr; /* Receive Data FIFO Reset (WO) */ 51 u32 rdfo; /* Receive Data FIFO Occupancy (RO) */ 52 u32 rdfd; /* Receive Data FIFO 32bit wide Data read port (RO) */ 53 u32 rlf; /* Receive Length FIFO (RO) */ 54 u32 llr; /* LocalLink Reset (WO) */ 55 }; 56 57 /* Interrupt Status Register (ISR), [1] p11 */ 58 #define LL_FIFO_ISR_RPURE (1 << 31) /* Receive Packet Underrun Read Err */ 59 #define LL_FIFO_ISR_RPORE (1 << 30) /* Receive Packet Overrun Read Err */ 60 #define LL_FIFO_ISR_RPUE (1 << 29) /* Receive Packet Underrun Error */ 61 #define LL_FIFO_ISR_TPOE (1 << 28) /* Transmit Packet Overrun Error */ 62 #define LL_FIFO_ISR_TC (1 << 27) /* Transmit Complete */ 63 #define LL_FIFO_ISR_RC (1 << 26) /* Receive Complete */ 64 #define LL_FIFO_ISR_TSE (1 << 25) /* Transmit Size Error */ 65 #define LL_FIFO_ISR_TRC (1 << 24) /* Transmit Reset Complete */ 66 #define LL_FIFO_ISR_RRC (1 << 23) /* Receive Reset Complete */ 67 68 /* Interrupt Enable Register (IER), [1] p12/p13 */ 69 #define LL_FIFO_IER_RPURE (1 << 31) /* Receive Packet Underrun Read Err */ 70 #define LL_FIFO_IER_RPORE (1 << 30) /* Receive Packet Overrun Read Err */ 71 #define LL_FIFO_IER_RPUE (1 << 29) /* Receive Packet Underrun Error */ 72 #define LL_FIFO_IER_TPOE (1 << 28) /* Transmit Packet Overrun Error */ 73 #define LL_FIFO_IER_TC (1 << 27) /* Transmit Complete */ 74 #define LL_FIFO_IER_RC (1 << 26) /* Receive Complete */ 75 #define LL_FIFO_IER_TSE (1 << 25) /* Transmit Size Error */ 76 #define LL_FIFO_IER_TRC (1 << 24) /* Transmit Reset Complete */ 77 #define LL_FIFO_IER_RRC (1 << 23) /* Receive Reset Complete */ 78 79 /* Transmit Data FIFO Reset (TDFR), [1] p13/p14 */ 80 #define LL_FIFO_TDFR_KEY 0x000000A5UL 81 82 /* Transmit Data FIFO Vacancy (TDFV), [1] p14 */ 83 #define LL_FIFO_TDFV_POS 0 84 #define LL_FIFO_TDFV_MASK (0x000001FFUL << LL_FIFO_TDFV_POS) 85 86 /* Transmit Length FIFO (TLF), [1] p16/p17 */ 87 #define LL_FIFO_TLF_POS 0 88 #define LL_FIFO_TLF_MASK (0x000007FFUL << LL_FIFO_TLF_POS) 89 #define LL_FIFO_TLF_MIN ((4 * sizeof(u32)) & LL_FIFO_TLF_MASK) 90 #define LL_FIFO_TLF_MAX ((510 * sizeof(u32)) & LL_FIFO_TLF_MASK) 91 92 /* Receive Data FIFO Reset (RDFR), [1] p15 */ 93 #define LL_FIFO_RDFR_KEY 0x000000A5UL 94 95 /* Receive Data FIFO Occupancy (RDFO), [1] p16 */ 96 #define LL_FIFO_RDFO_POS 0 97 #define LL_FIFO_RDFO_MASK (0x000001FFUL << LL_FIFO_RDFO_POS) 98 99 /* Receive Length FIFO (RLF), [1] p17/p18 */ 100 #define LL_FIFO_RLF_POS 0 101 #define LL_FIFO_RLF_MASK (0x000007FFUL << LL_FIFO_RLF_POS) 102 #define LL_FIFO_RLF_MIN ((4 * sizeof(uint32)) & LL_FIFO_RLF_MASK) 103 #define LL_FIFO_RLF_MAX ((510 * sizeof(uint32)) & LL_FIFO_RLF_MASK) 104 105 /* LocalLink Reset (LLR), [1] p18 */ 106 #define LL_FIFO_LLR_KEY 0x000000A5UL 107 108 109 /* reset FIFO and IRQ, disable interrupts */ 110 int ll_temac_reset_fifo(struct eth_device *dev); 111 112 /* receive buffered data from FIFO (polling ISR) */ 113 int ll_temac_recv_fifo(struct eth_device *dev); 114 115 /* send buffered data to FIFO */ 116 int ll_temac_send_fifo(struct eth_device *dev, void *packet, int length); 117 118 #endif /* _XILINX_LL_TEMAC_FIFO_ */ 119