1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Xilinx xps_ll_temac ethernet driver for u-boot 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * FIFO sub-controller interface 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2011 - 2012 Stephan Linz <linz@li-pro.net> 7*4882a593Smuzhiyun * Copyright (C) 2008 - 2011 Michal Simek <monstr@monstr.eu> 8*4882a593Smuzhiyun * Copyright (C) 2008 - 2011 PetaLogix 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver 11*4882a593Smuzhiyun * Copyright (C) 2008 Nissin Systems Co.,Ltd. 12*4882a593Smuzhiyun * March 2008 created 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * [0]: http://www.xilinx.com/support/documentation 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * [S]: [0]/ip_documentation/xps_ll_temac.pdf 19*4882a593Smuzhiyun * [A]: [0]/application_notes/xapp1041.pdf 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun #ifndef _XILINX_LL_TEMAC_FIFO_ 22*4882a593Smuzhiyun #define _XILINX_LL_TEMAC_FIFO_ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #include <net.h> 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #include <asm/types.h> 27*4882a593Smuzhiyun #include <asm/byteorder.h> 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #if !defined(__BIG_ENDIAN) 30*4882a593Smuzhiyun # error LL_TEMAC requires big endianess 31*4882a593Smuzhiyun #endif 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * FIFO Register Definition 35*4882a593Smuzhiyun * 36*4882a593Smuzhiyun * Used for memory mapped access from and to (Rd/Td) the LocalLink (LL) 37*4882a593Smuzhiyun * Tri-Mode Ether MAC (TEMAC) via the 2 kb full duplex FIFO Controller, 38*4882a593Smuzhiyun * one for each. 39*4882a593Smuzhiyun * 40*4882a593Smuzhiyun * [1]: [0]/ip_documentation/xps_ll_fifo.pdf 41*4882a593Smuzhiyun * page 10, Registers Definition 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun struct fifo_ctrl { 44*4882a593Smuzhiyun u32 isr; /* Interrupt Status Register (RW) */ 45*4882a593Smuzhiyun u32 ier; /* Interrupt Enable Register (RW) */ 46*4882a593Smuzhiyun u32 tdfr; /* Transmit Data FIFO Reset (WO) */ 47*4882a593Smuzhiyun u32 tdfv; /* Transmit Data FIFO Vacancy (RO) */ 48*4882a593Smuzhiyun u32 tdfd; /* Transmit Data FIFO 32bit wide Data write port (WO) */ 49*4882a593Smuzhiyun u32 tlf; /* Transmit Length FIFO (WO) */ 50*4882a593Smuzhiyun u32 rdfr; /* Receive Data FIFO Reset (WO) */ 51*4882a593Smuzhiyun u32 rdfo; /* Receive Data FIFO Occupancy (RO) */ 52*4882a593Smuzhiyun u32 rdfd; /* Receive Data FIFO 32bit wide Data read port (RO) */ 53*4882a593Smuzhiyun u32 rlf; /* Receive Length FIFO (RO) */ 54*4882a593Smuzhiyun u32 llr; /* LocalLink Reset (WO) */ 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* Interrupt Status Register (ISR), [1] p11 */ 58*4882a593Smuzhiyun #define LL_FIFO_ISR_RPURE (1 << 31) /* Receive Packet Underrun Read Err */ 59*4882a593Smuzhiyun #define LL_FIFO_ISR_RPORE (1 << 30) /* Receive Packet Overrun Read Err */ 60*4882a593Smuzhiyun #define LL_FIFO_ISR_RPUE (1 << 29) /* Receive Packet Underrun Error */ 61*4882a593Smuzhiyun #define LL_FIFO_ISR_TPOE (1 << 28) /* Transmit Packet Overrun Error */ 62*4882a593Smuzhiyun #define LL_FIFO_ISR_TC (1 << 27) /* Transmit Complete */ 63*4882a593Smuzhiyun #define LL_FIFO_ISR_RC (1 << 26) /* Receive Complete */ 64*4882a593Smuzhiyun #define LL_FIFO_ISR_TSE (1 << 25) /* Transmit Size Error */ 65*4882a593Smuzhiyun #define LL_FIFO_ISR_TRC (1 << 24) /* Transmit Reset Complete */ 66*4882a593Smuzhiyun #define LL_FIFO_ISR_RRC (1 << 23) /* Receive Reset Complete */ 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* Interrupt Enable Register (IER), [1] p12/p13 */ 69*4882a593Smuzhiyun #define LL_FIFO_IER_RPURE (1 << 31) /* Receive Packet Underrun Read Err */ 70*4882a593Smuzhiyun #define LL_FIFO_IER_RPORE (1 << 30) /* Receive Packet Overrun Read Err */ 71*4882a593Smuzhiyun #define LL_FIFO_IER_RPUE (1 << 29) /* Receive Packet Underrun Error */ 72*4882a593Smuzhiyun #define LL_FIFO_IER_TPOE (1 << 28) /* Transmit Packet Overrun Error */ 73*4882a593Smuzhiyun #define LL_FIFO_IER_TC (1 << 27) /* Transmit Complete */ 74*4882a593Smuzhiyun #define LL_FIFO_IER_RC (1 << 26) /* Receive Complete */ 75*4882a593Smuzhiyun #define LL_FIFO_IER_TSE (1 << 25) /* Transmit Size Error */ 76*4882a593Smuzhiyun #define LL_FIFO_IER_TRC (1 << 24) /* Transmit Reset Complete */ 77*4882a593Smuzhiyun #define LL_FIFO_IER_RRC (1 << 23) /* Receive Reset Complete */ 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* Transmit Data FIFO Reset (TDFR), [1] p13/p14 */ 80*4882a593Smuzhiyun #define LL_FIFO_TDFR_KEY 0x000000A5UL 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* Transmit Data FIFO Vacancy (TDFV), [1] p14 */ 83*4882a593Smuzhiyun #define LL_FIFO_TDFV_POS 0 84*4882a593Smuzhiyun #define LL_FIFO_TDFV_MASK (0x000001FFUL << LL_FIFO_TDFV_POS) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* Transmit Length FIFO (TLF), [1] p16/p17 */ 87*4882a593Smuzhiyun #define LL_FIFO_TLF_POS 0 88*4882a593Smuzhiyun #define LL_FIFO_TLF_MASK (0x000007FFUL << LL_FIFO_TLF_POS) 89*4882a593Smuzhiyun #define LL_FIFO_TLF_MIN ((4 * sizeof(u32)) & LL_FIFO_TLF_MASK) 90*4882a593Smuzhiyun #define LL_FIFO_TLF_MAX ((510 * sizeof(u32)) & LL_FIFO_TLF_MASK) 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* Receive Data FIFO Reset (RDFR), [1] p15 */ 93*4882a593Smuzhiyun #define LL_FIFO_RDFR_KEY 0x000000A5UL 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* Receive Data FIFO Occupancy (RDFO), [1] p16 */ 96*4882a593Smuzhiyun #define LL_FIFO_RDFO_POS 0 97*4882a593Smuzhiyun #define LL_FIFO_RDFO_MASK (0x000001FFUL << LL_FIFO_RDFO_POS) 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* Receive Length FIFO (RLF), [1] p17/p18 */ 100*4882a593Smuzhiyun #define LL_FIFO_RLF_POS 0 101*4882a593Smuzhiyun #define LL_FIFO_RLF_MASK (0x000007FFUL << LL_FIFO_RLF_POS) 102*4882a593Smuzhiyun #define LL_FIFO_RLF_MIN ((4 * sizeof(uint32)) & LL_FIFO_RLF_MASK) 103*4882a593Smuzhiyun #define LL_FIFO_RLF_MAX ((510 * sizeof(uint32)) & LL_FIFO_RLF_MASK) 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* LocalLink Reset (LLR), [1] p18 */ 106*4882a593Smuzhiyun #define LL_FIFO_LLR_KEY 0x000000A5UL 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* reset FIFO and IRQ, disable interrupts */ 110*4882a593Smuzhiyun int ll_temac_reset_fifo(struct eth_device *dev); 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* receive buffered data from FIFO (polling ISR) */ 113*4882a593Smuzhiyun int ll_temac_recv_fifo(struct eth_device *dev); 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* send buffered data to FIFO */ 116*4882a593Smuzhiyun int ll_temac_send_fifo(struct eth_device *dev, void *packet, int length); 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #endif /* _XILINX_LL_TEMAC_FIFO_ */ 119