1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * pic32_mdio.c: PIC32 MDIO/MII driver, part of pic32_eth.c.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright 2015 Microchip Inc.
5*4882a593Smuzhiyun * Purna Chandra Mandal <purna.mandal@microchip.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <phy.h>
11*4882a593Smuzhiyun #include <miiphy.h>
12*4882a593Smuzhiyun #include <errno.h>
13*4882a593Smuzhiyun #include <wait_bit.h>
14*4882a593Smuzhiyun #include <asm/io.h>
15*4882a593Smuzhiyun #include "pic32_eth.h"
16*4882a593Smuzhiyun
pic32_mdio_write(struct mii_dev * bus,int addr,int dev_addr,int reg,u16 value)17*4882a593Smuzhiyun static int pic32_mdio_write(struct mii_dev *bus,
18*4882a593Smuzhiyun int addr, int dev_addr,
19*4882a593Smuzhiyun int reg, u16 value)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun u32 v;
22*4882a593Smuzhiyun struct pic32_mii_regs *mii_regs = bus->priv;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* Wait for the previous operation to finish */
25*4882a593Smuzhiyun wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
26*4882a593Smuzhiyun false, CONFIG_SYS_HZ, true);
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* Put phyaddr and regaddr into MIIMADD */
29*4882a593Smuzhiyun v = (addr << MIIMADD_PHYADDR_SHIFT) | (reg & MIIMADD_REGADDR);
30*4882a593Smuzhiyun writel(v, &mii_regs->madr.raw);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* Initiate a write command */
33*4882a593Smuzhiyun writel(value, &mii_regs->mwtd.raw);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* Wait 30 clock cycles for busy flag to be set */
36*4882a593Smuzhiyun udelay(12);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /* Wait for write to complete */
39*4882a593Smuzhiyun wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
40*4882a593Smuzhiyun false, CONFIG_SYS_HZ, true);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun return 0;
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
pic32_mdio_read(struct mii_dev * bus,int addr,int devaddr,int reg)45*4882a593Smuzhiyun static int pic32_mdio_read(struct mii_dev *bus, int addr, int devaddr, int reg)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun u32 v;
48*4882a593Smuzhiyun struct pic32_mii_regs *mii_regs = bus->priv;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* Wait for the previous operation to finish */
51*4882a593Smuzhiyun wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
52*4882a593Smuzhiyun false, CONFIG_SYS_HZ, true);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /* Put phyaddr and regaddr into MIIMADD */
55*4882a593Smuzhiyun v = (addr << MIIMADD_PHYADDR_SHIFT) | (reg & MIIMADD_REGADDR);
56*4882a593Smuzhiyun writel(v, &mii_regs->madr.raw);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* Initiate a read command */
59*4882a593Smuzhiyun writel(MIIMCMD_READ, &mii_regs->mcmd.raw);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* Wait 30 clock cycles for busy flag to be set */
62*4882a593Smuzhiyun udelay(12);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /* Wait for read to complete */
65*4882a593Smuzhiyun wait_for_bit_le32(&mii_regs->mind.raw,
66*4882a593Smuzhiyun MIIMIND_NOTVALID | MIIMIND_BUSY,
67*4882a593Smuzhiyun false, CONFIG_SYS_HZ, false);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /* Clear the command register */
70*4882a593Smuzhiyun writel(0, &mii_regs->mcmd.raw);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* Grab the value read from the PHY */
73*4882a593Smuzhiyun v = readl(&mii_regs->mrdd.raw);
74*4882a593Smuzhiyun return v;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
pic32_mdio_reset(struct mii_dev * bus)77*4882a593Smuzhiyun static int pic32_mdio_reset(struct mii_dev *bus)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun struct pic32_mii_regs *mii_regs = bus->priv;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /* Reset MII (due to new addresses) */
82*4882a593Smuzhiyun writel(MIIMCFG_RSTMGMT, &mii_regs->mcfg.raw);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* Wait for the operation to finish */
85*4882a593Smuzhiyun wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
86*4882a593Smuzhiyun false, CONFIG_SYS_HZ, true);
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun /* Clear reset bit */
89*4882a593Smuzhiyun writel(0, &mii_regs->mcfg);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun /* Wait for the operation to finish */
92*4882a593Smuzhiyun wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
93*4882a593Smuzhiyun false, CONFIG_SYS_HZ, true);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /* Set the MII Management Clock (MDC) - no faster than 2.5 MHz */
96*4882a593Smuzhiyun writel(MIIMCFG_CLKSEL_DIV40, &mii_regs->mcfg.raw);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun /* Wait for the operation to finish */
99*4882a593Smuzhiyun wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
100*4882a593Smuzhiyun false, CONFIG_SYS_HZ, true);
101*4882a593Smuzhiyun return 0;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
pic32_mdio_init(const char * name,ulong ioaddr)104*4882a593Smuzhiyun int pic32_mdio_init(const char *name, ulong ioaddr)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun struct mii_dev *bus;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun bus = mdio_alloc();
109*4882a593Smuzhiyun if (!bus) {
110*4882a593Smuzhiyun printf("Failed to allocate PIC32-MDIO bus\n");
111*4882a593Smuzhiyun return -ENOMEM;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun bus->read = pic32_mdio_read;
115*4882a593Smuzhiyun bus->write = pic32_mdio_write;
116*4882a593Smuzhiyun bus->reset = pic32_mdio_reset;
117*4882a593Smuzhiyun strncpy(bus->name, name, sizeof(bus->name));
118*4882a593Smuzhiyun bus->priv = (void *)ioaddr;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun return mdio_register(bus);
121*4882a593Smuzhiyun }
122