1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Teranetics PHY drivers
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright 2010-2011 Freescale Semiconductor, Inc.
7*4882a593Smuzhiyun * author Andy Fleming
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun #include <config.h>
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <phy.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #ifndef CONFIG_PHYLIB_10G
14*4882a593Smuzhiyun #error The Teranetics PHY needs 10G support
15*4882a593Smuzhiyun #endif
16*4882a593Smuzhiyun
tn2020_config(struct phy_device * phydev)17*4882a593Smuzhiyun int tn2020_config(struct phy_device *phydev)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun if (phydev->port == PORT_FIBRE) {
20*4882a593Smuzhiyun unsigned short restart_an = (MDIO_AN_CTRL1_RESTART |
21*4882a593Smuzhiyun MDIO_AN_CTRL1_ENABLE |
22*4882a593Smuzhiyun MDIO_AN_CTRL1_XNP);
23*4882a593Smuzhiyun u8 phy_hwversion;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /*
26*4882a593Smuzhiyun * bit 15:12 of register 30.32 indicates PHY hardware
27*4882a593Smuzhiyun * version. It can be used to distinguish TN80xx from
28*4882a593Smuzhiyun * TN2020. TN2020 needs write 0x2 to 30.93, but TN80xx
29*4882a593Smuzhiyun * needs 0x1.
30*4882a593Smuzhiyun */
31*4882a593Smuzhiyun phy_hwversion = (phy_read(phydev, 30, 32) >> 12) & 0xf;
32*4882a593Smuzhiyun if (phy_hwversion <= 3) {
33*4882a593Smuzhiyun phy_write(phydev, 30, 93, 2);
34*4882a593Smuzhiyun phy_write(phydev, MDIO_MMD_AN, MDIO_CTRL1, restart_an);
35*4882a593Smuzhiyun } else {
36*4882a593Smuzhiyun phy_write(phydev, 30, 93, 1);
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun return 0;
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
tn2020_startup(struct phy_device * phydev)43*4882a593Smuzhiyun int tn2020_startup(struct phy_device *phydev)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun unsigned int timeout = 5 * 1000; /* 5 second timeout */
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define MDIO_PHYXS_LANE_READY (MDIO_PHYXS_LNSTAT_SYNC0 | \
48*4882a593Smuzhiyun MDIO_PHYXS_LNSTAT_SYNC1 | \
49*4882a593Smuzhiyun MDIO_PHYXS_LNSTAT_SYNC2 | \
50*4882a593Smuzhiyun MDIO_PHYXS_LNSTAT_SYNC3 | \
51*4882a593Smuzhiyun MDIO_PHYXS_LNSTAT_ALIGN)
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /*
54*4882a593Smuzhiyun * Wait for the XAUI-SERDES lanes to align first. Under normal
55*4882a593Smuzhiyun * circumstances, this can take up to three seconds.
56*4882a593Smuzhiyun */
57*4882a593Smuzhiyun while (--timeout) {
58*4882a593Smuzhiyun int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_LNSTAT);
59*4882a593Smuzhiyun if (reg < 0) {
60*4882a593Smuzhiyun printf("TN2020: Error reading from PHY at "
61*4882a593Smuzhiyun "address %u\n", phydev->addr);
62*4882a593Smuzhiyun break;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun if ((reg & MDIO_PHYXS_LANE_READY) == MDIO_PHYXS_LANE_READY)
65*4882a593Smuzhiyun break;
66*4882a593Smuzhiyun udelay(1000);
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun if (!timeout) {
69*4882a593Smuzhiyun /*
70*4882a593Smuzhiyun * A timeout is bad, but it may not be fatal, so don't
71*4882a593Smuzhiyun * return an error. Display a warning instead.
72*4882a593Smuzhiyun */
73*4882a593Smuzhiyun printf("TN2020: Timeout waiting for PHY at address %u to "
74*4882a593Smuzhiyun "align.\n", phydev->addr);
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun if (phydev->port != PORT_FIBRE)
78*4882a593Smuzhiyun return gen10g_startup(phydev);
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /*
81*4882a593Smuzhiyun * The TN2020 only pretends to support fiber.
82*4882a593Smuzhiyun * It works, but it doesn't look like it works,
83*4882a593Smuzhiyun * so the link status reports no link.
84*4882a593Smuzhiyun */
85*4882a593Smuzhiyun phydev->link = 1;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* For now just lie and say it's 10G all the time */
88*4882a593Smuzhiyun phydev->speed = SPEED_10000;
89*4882a593Smuzhiyun phydev->duplex = DUPLEX_FULL;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun return 0;
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun struct phy_driver tn2020_driver = {
95*4882a593Smuzhiyun .name = "Teranetics TN2020",
96*4882a593Smuzhiyun .uid = PHY_UID_TN2020,
97*4882a593Smuzhiyun .mask = 0xfffffff0,
98*4882a593Smuzhiyun .features = PHY_10G_FEATURES,
99*4882a593Smuzhiyun .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
100*4882a593Smuzhiyun MDIO_DEVS_PHYXS | MDIO_DEVS_AN |
101*4882a593Smuzhiyun MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2),
102*4882a593Smuzhiyun .config = &tn2020_config,
103*4882a593Smuzhiyun .startup = &tn2020_startup,
104*4882a593Smuzhiyun .shutdown = &gen10g_shutdown,
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun
phy_teranetics_init(void)107*4882a593Smuzhiyun int phy_teranetics_init(void)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun phy_register(&tn2020_driver);
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun return 0;
112*4882a593Smuzhiyun }
113