1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Atheros PHY drivers
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright 2011, 2013 Freescale Semiconductor, Inc.
7*4882a593Smuzhiyun * author Andy Fleming
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun #include <phy.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #define AR803x_PHY_DEBUG_ADDR_REG 0x1d
12*4882a593Smuzhiyun #define AR803x_PHY_DEBUG_DATA_REG 0x1e
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define AR803x_DEBUG_REG_5 0x5
15*4882a593Smuzhiyun #define AR803x_RGMII_TX_CLK_DLY 0x100
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define AR803x_DEBUG_REG_0 0x0
18*4882a593Smuzhiyun #define AR803x_RGMII_RX_CLK_DLY 0x8000
19*4882a593Smuzhiyun
ar8021_config(struct phy_device * phydev)20*4882a593Smuzhiyun static int ar8021_config(struct phy_device *phydev)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
23*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun phydev->supported = phydev->drv->features;
26*4882a593Smuzhiyun return 0;
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun
ar8031_config(struct phy_device * phydev)29*4882a593Smuzhiyun static int ar8031_config(struct phy_device *phydev)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
32*4882a593Smuzhiyun phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
33*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
34*4882a593Smuzhiyun AR803x_DEBUG_REG_5);
35*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
36*4882a593Smuzhiyun AR803x_RGMII_TX_CLK_DLY);
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
40*4882a593Smuzhiyun phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
41*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
42*4882a593Smuzhiyun AR803x_DEBUG_REG_0);
43*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
44*4882a593Smuzhiyun AR803x_RGMII_RX_CLK_DLY);
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun phydev->supported = phydev->drv->features;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun genphy_config_aneg(phydev);
50*4882a593Smuzhiyun genphy_restart_aneg(phydev);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun return 0;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
ar8035_config(struct phy_device * phydev)55*4882a593Smuzhiyun static int ar8035_config(struct phy_device *phydev)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun int regval;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007);
60*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
61*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
62*4882a593Smuzhiyun regval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
63*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018));
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
66*4882a593Smuzhiyun regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
67*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100));
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
70*4882a593Smuzhiyun (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
71*4882a593Smuzhiyun /* select debug reg 5 */
72*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x5);
73*4882a593Smuzhiyun /* enable tx delay */
74*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x0100);
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
78*4882a593Smuzhiyun (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) {
79*4882a593Smuzhiyun /* select debug reg 0 */
80*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x0);
81*4882a593Smuzhiyun /* enable rx delay */
82*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x8000);
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun phydev->supported = phydev->drv->features;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun genphy_config_aneg(phydev);
88*4882a593Smuzhiyun genphy_restart_aneg(phydev);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun return 0;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun static struct phy_driver AR8021_driver = {
94*4882a593Smuzhiyun .name = "AR8021",
95*4882a593Smuzhiyun .uid = 0x4dd040,
96*4882a593Smuzhiyun .mask = 0x4ffff0,
97*4882a593Smuzhiyun .features = PHY_GBIT_FEATURES,
98*4882a593Smuzhiyun .config = ar8021_config,
99*4882a593Smuzhiyun .startup = genphy_startup,
100*4882a593Smuzhiyun .shutdown = genphy_shutdown,
101*4882a593Smuzhiyun };
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun static struct phy_driver AR8031_driver = {
104*4882a593Smuzhiyun .name = "AR8031/AR8033",
105*4882a593Smuzhiyun .uid = 0x4dd074,
106*4882a593Smuzhiyun .mask = 0xffffffef,
107*4882a593Smuzhiyun .features = PHY_GBIT_FEATURES,
108*4882a593Smuzhiyun .config = ar8031_config,
109*4882a593Smuzhiyun .startup = genphy_startup,
110*4882a593Smuzhiyun .shutdown = genphy_shutdown,
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun static struct phy_driver AR8035_driver = {
114*4882a593Smuzhiyun .name = "AR8035",
115*4882a593Smuzhiyun .uid = 0x4dd072,
116*4882a593Smuzhiyun .mask = 0xffffffef,
117*4882a593Smuzhiyun .features = PHY_GBIT_FEATURES,
118*4882a593Smuzhiyun .config = ar8035_config,
119*4882a593Smuzhiyun .startup = genphy_startup,
120*4882a593Smuzhiyun .shutdown = genphy_shutdown,
121*4882a593Smuzhiyun };
122*4882a593Smuzhiyun
phy_atheros_init(void)123*4882a593Smuzhiyun int phy_atheros_init(void)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun phy_register(&AR8021_driver);
126*4882a593Smuzhiyun phy_register(&AR8031_driver);
127*4882a593Smuzhiyun phy_register(&AR8035_driver);
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun return 0;
130*4882a593Smuzhiyun }
131