xref: /OK3568_Linux_fs/u-boot/drivers/net/phy/aquantia.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Aquantia PHY drivers
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Copyright 2014 Freescale Semiconductor, Inc.
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun #include <config.h>
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <phy.h>
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #ifndef CONFIG_PHYLIB_10G
13*4882a593Smuzhiyun #error The Aquantia PHY needs 10G support
14*4882a593Smuzhiyun #endif
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #define AQUNTIA_10G_CTL		0x20
17*4882a593Smuzhiyun #define AQUNTIA_VENDOR_P1	0xc400
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #define AQUNTIA_SPEED_LSB_MASK	0x2000
20*4882a593Smuzhiyun #define AQUNTIA_SPEED_MSB_MASK	0x40
21*4882a593Smuzhiyun 
aquantia_config(struct phy_device * phydev)22*4882a593Smuzhiyun int aquantia_config(struct phy_device *phydev)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun 	u32 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun 	if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
27*4882a593Smuzhiyun 		/* 1000BASE-T mode */
28*4882a593Smuzhiyun 		phydev->advertising = SUPPORTED_1000baseT_Full;
29*4882a593Smuzhiyun 		phydev->supported = phydev->advertising;
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun 		val = (val & ~AQUNTIA_SPEED_LSB_MASK) | AQUNTIA_SPEED_MSB_MASK;
32*4882a593Smuzhiyun 		phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
33*4882a593Smuzhiyun 	} else if (phydev->interface == PHY_INTERFACE_MODE_XGMII) {
34*4882a593Smuzhiyun 		/* 10GBASE-T mode */
35*4882a593Smuzhiyun 		phydev->advertising = SUPPORTED_10000baseT_Full;
36*4882a593Smuzhiyun 		phydev->supported = phydev->advertising;
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun 		if (!(val & AQUNTIA_SPEED_LSB_MASK) ||
39*4882a593Smuzhiyun 		    !(val & AQUNTIA_SPEED_MSB_MASK))
40*4882a593Smuzhiyun 			phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR,
41*4882a593Smuzhiyun 				  AQUNTIA_SPEED_LSB_MASK |
42*4882a593Smuzhiyun 				  AQUNTIA_SPEED_MSB_MASK);
43*4882a593Smuzhiyun 	} else if (phydev->interface == PHY_INTERFACE_MODE_SGMII_2500) {
44*4882a593Smuzhiyun 		/* 2.5GBASE-T mode */
45*4882a593Smuzhiyun 		phydev->advertising = SUPPORTED_1000baseT_Full;
46*4882a593Smuzhiyun 		phydev->supported = phydev->advertising;
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun 		phy_write(phydev, MDIO_MMD_AN, AQUNTIA_10G_CTL, 1);
49*4882a593Smuzhiyun 		phy_write(phydev, MDIO_MMD_AN, AQUNTIA_VENDOR_P1, 0x9440);
50*4882a593Smuzhiyun 	} else if (phydev->interface == PHY_INTERFACE_MODE_MII) {
51*4882a593Smuzhiyun 		/* 100BASE-TX mode */
52*4882a593Smuzhiyun 		phydev->advertising = SUPPORTED_100baseT_Full;
53*4882a593Smuzhiyun 		phydev->supported = phydev->advertising;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 		val = (val & ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK;
56*4882a593Smuzhiyun 		phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
57*4882a593Smuzhiyun 	}
58*4882a593Smuzhiyun 	return 0;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun 
aquantia_startup(struct phy_device * phydev)61*4882a593Smuzhiyun int aquantia_startup(struct phy_device *phydev)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun 	u32 reg, speed;
64*4882a593Smuzhiyun 	int i = 0;
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 	phydev->duplex = DUPLEX_FULL;
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun 	/* if the AN is still in progress, wait till timeout. */
69*4882a593Smuzhiyun 	phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
70*4882a593Smuzhiyun 	reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
71*4882a593Smuzhiyun 	if (!(reg & MDIO_AN_STAT1_COMPLETE)) {
72*4882a593Smuzhiyun 		printf("%s Waiting for PHY auto negotiation to complete",
73*4882a593Smuzhiyun 		       phydev->dev->name);
74*4882a593Smuzhiyun 		do {
75*4882a593Smuzhiyun 			udelay(1000);
76*4882a593Smuzhiyun 			reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
77*4882a593Smuzhiyun 			if ((i++ % 500) == 0)
78*4882a593Smuzhiyun 				printf(".");
79*4882a593Smuzhiyun 		} while (!(reg & MDIO_AN_STAT1_COMPLETE) &&
80*4882a593Smuzhiyun 			 i < (4 * PHY_ANEG_TIMEOUT));
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 		if (i > PHY_ANEG_TIMEOUT)
83*4882a593Smuzhiyun 			printf(" TIMEOUT !\n");
84*4882a593Smuzhiyun 	}
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	/* Read twice because link state is latched and a
87*4882a593Smuzhiyun 	 * read moves the current state into the register */
88*4882a593Smuzhiyun 	phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
89*4882a593Smuzhiyun 	reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
90*4882a593Smuzhiyun 	if (reg < 0 || !(reg & MDIO_STAT1_LSTATUS))
91*4882a593Smuzhiyun 		phydev->link = 0;
92*4882a593Smuzhiyun 	else
93*4882a593Smuzhiyun 		phydev->link = 1;
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
96*4882a593Smuzhiyun 	if (speed & AQUNTIA_SPEED_MSB_MASK) {
97*4882a593Smuzhiyun 		if (speed & AQUNTIA_SPEED_LSB_MASK)
98*4882a593Smuzhiyun 			phydev->speed = SPEED_10000;
99*4882a593Smuzhiyun 		else
100*4882a593Smuzhiyun 			phydev->speed = SPEED_1000;
101*4882a593Smuzhiyun 	} else {
102*4882a593Smuzhiyun 		if (speed & AQUNTIA_SPEED_LSB_MASK)
103*4882a593Smuzhiyun 			phydev->speed = SPEED_100;
104*4882a593Smuzhiyun 		else
105*4882a593Smuzhiyun 			phydev->speed = SPEED_10;
106*4882a593Smuzhiyun 	}
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	return 0;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun struct phy_driver aq1202_driver = {
112*4882a593Smuzhiyun 	.name = "Aquantia AQ1202",
113*4882a593Smuzhiyun 	.uid = 0x3a1b445,
114*4882a593Smuzhiyun 	.mask = 0xfffffff0,
115*4882a593Smuzhiyun 	.features = PHY_10G_FEATURES,
116*4882a593Smuzhiyun 	.mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
117*4882a593Smuzhiyun 			MDIO_MMD_PHYXS | MDIO_MMD_AN |
118*4882a593Smuzhiyun 			MDIO_MMD_VEND1),
119*4882a593Smuzhiyun 	.config = &aquantia_config,
120*4882a593Smuzhiyun 	.startup = &aquantia_startup,
121*4882a593Smuzhiyun 	.shutdown = &gen10g_shutdown,
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun struct phy_driver aq2104_driver = {
125*4882a593Smuzhiyun 	.name = "Aquantia AQ2104",
126*4882a593Smuzhiyun 	.uid = 0x3a1b460,
127*4882a593Smuzhiyun 	.mask = 0xfffffff0,
128*4882a593Smuzhiyun 	.features = PHY_10G_FEATURES,
129*4882a593Smuzhiyun 	.mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
130*4882a593Smuzhiyun 			MDIO_MMD_PHYXS | MDIO_MMD_AN |
131*4882a593Smuzhiyun 			MDIO_MMD_VEND1),
132*4882a593Smuzhiyun 	.config = &aquantia_config,
133*4882a593Smuzhiyun 	.startup = &aquantia_startup,
134*4882a593Smuzhiyun 	.shutdown = &gen10g_shutdown,
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun struct phy_driver aqr105_driver = {
138*4882a593Smuzhiyun 	.name = "Aquantia AQR105",
139*4882a593Smuzhiyun 	.uid = 0x3a1b4a2,
140*4882a593Smuzhiyun 	.mask = 0xfffffff0,
141*4882a593Smuzhiyun 	.features = PHY_10G_FEATURES,
142*4882a593Smuzhiyun 	.mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
143*4882a593Smuzhiyun 			MDIO_MMD_PHYXS | MDIO_MMD_AN |
144*4882a593Smuzhiyun 			MDIO_MMD_VEND1),
145*4882a593Smuzhiyun 	.config = &aquantia_config,
146*4882a593Smuzhiyun 	.startup = &aquantia_startup,
147*4882a593Smuzhiyun 	.shutdown = &gen10g_shutdown,
148*4882a593Smuzhiyun };
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun struct phy_driver aqr106_driver = {
151*4882a593Smuzhiyun 	.name = "Aquantia AQR106",
152*4882a593Smuzhiyun 	.uid = 0x3a1b4d0,
153*4882a593Smuzhiyun 	.mask = 0xfffffff0,
154*4882a593Smuzhiyun 	.features = PHY_10G_FEATURES,
155*4882a593Smuzhiyun 	.mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
156*4882a593Smuzhiyun 			MDIO_MMD_PHYXS | MDIO_MMD_AN |
157*4882a593Smuzhiyun 			MDIO_MMD_VEND1),
158*4882a593Smuzhiyun 	.config = &aquantia_config,
159*4882a593Smuzhiyun 	.startup = &aquantia_startup,
160*4882a593Smuzhiyun 	.shutdown = &gen10g_shutdown,
161*4882a593Smuzhiyun };
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun struct phy_driver aqr107_driver = {
164*4882a593Smuzhiyun 	.name = "Aquantia AQR107",
165*4882a593Smuzhiyun 	.uid = 0x3a1b4e0,
166*4882a593Smuzhiyun 	.mask = 0xfffffff0,
167*4882a593Smuzhiyun 	.features = PHY_10G_FEATURES,
168*4882a593Smuzhiyun 	.mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
169*4882a593Smuzhiyun 			MDIO_MMD_PHYXS | MDIO_MMD_AN |
170*4882a593Smuzhiyun 			MDIO_MMD_VEND1),
171*4882a593Smuzhiyun 	.config = &aquantia_config,
172*4882a593Smuzhiyun 	.startup = &aquantia_startup,
173*4882a593Smuzhiyun 	.shutdown = &gen10g_shutdown,
174*4882a593Smuzhiyun };
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun struct phy_driver aqr405_driver = {
177*4882a593Smuzhiyun 	.name = "Aquantia AQR405",
178*4882a593Smuzhiyun 	.uid = 0x3a1b4b2,
179*4882a593Smuzhiyun 	.mask = 0xfffffff0,
180*4882a593Smuzhiyun 	.features = PHY_10G_FEATURES,
181*4882a593Smuzhiyun 	.mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
182*4882a593Smuzhiyun 		 MDIO_MMD_PHYXS | MDIO_MMD_AN |
183*4882a593Smuzhiyun 		 MDIO_MMD_VEND1),
184*4882a593Smuzhiyun 	.config = &aquantia_config,
185*4882a593Smuzhiyun 	.startup = &aquantia_startup,
186*4882a593Smuzhiyun 	.shutdown = &gen10g_shutdown,
187*4882a593Smuzhiyun };
188*4882a593Smuzhiyun 
phy_aquantia_init(void)189*4882a593Smuzhiyun int phy_aquantia_init(void)
190*4882a593Smuzhiyun {
191*4882a593Smuzhiyun 	phy_register(&aq1202_driver);
192*4882a593Smuzhiyun 	phy_register(&aq2104_driver);
193*4882a593Smuzhiyun 	phy_register(&aqr105_driver);
194*4882a593Smuzhiyun 	phy_register(&aqr106_driver);
195*4882a593Smuzhiyun 	phy_register(&aqr107_driver);
196*4882a593Smuzhiyun 	phy_register(&aqr405_driver);
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	return 0;
199*4882a593Smuzhiyun }
200