xref: /OK3568_Linux_fs/u-boot/drivers/net/macb.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (C) 2005-2006 Atmel Corporation
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun #ifndef __DRIVERS_MACB_H__
7*4882a593Smuzhiyun #define __DRIVERS_MACB_H__
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun /* MACB register offsets */
10*4882a593Smuzhiyun #define MACB_NCR				0x0000
11*4882a593Smuzhiyun #define MACB_NCFGR				0x0004
12*4882a593Smuzhiyun #define MACB_NSR				0x0008
13*4882a593Smuzhiyun #define GEM_UR					0x000c
14*4882a593Smuzhiyun #define MACB_TSR				0x0014
15*4882a593Smuzhiyun #define MACB_RBQP				0x0018
16*4882a593Smuzhiyun #define MACB_TBQP				0x001c
17*4882a593Smuzhiyun #define MACB_RSR				0x0020
18*4882a593Smuzhiyun #define MACB_ISR				0x0024
19*4882a593Smuzhiyun #define MACB_IER				0x0028
20*4882a593Smuzhiyun #define MACB_IDR				0x002c
21*4882a593Smuzhiyun #define MACB_IMR				0x0030
22*4882a593Smuzhiyun #define MACB_MAN				0x0034
23*4882a593Smuzhiyun #define MACB_PTR				0x0038
24*4882a593Smuzhiyun #define MACB_PFR				0x003c
25*4882a593Smuzhiyun #define MACB_FTO				0x0040
26*4882a593Smuzhiyun #define MACB_SCF				0x0044
27*4882a593Smuzhiyun #define MACB_MCF				0x0048
28*4882a593Smuzhiyun #define MACB_FRO				0x004c
29*4882a593Smuzhiyun #define MACB_FCSE				0x0050
30*4882a593Smuzhiyun #define MACB_ALE				0x0054
31*4882a593Smuzhiyun #define MACB_DTF				0x0058
32*4882a593Smuzhiyun #define MACB_LCOL				0x005c
33*4882a593Smuzhiyun #define MACB_EXCOL				0x0060
34*4882a593Smuzhiyun #define MACB_TUND				0x0064
35*4882a593Smuzhiyun #define MACB_CSE				0x0068
36*4882a593Smuzhiyun #define MACB_RRE				0x006c
37*4882a593Smuzhiyun #define MACB_ROVR				0x0070
38*4882a593Smuzhiyun #define MACB_RSE				0x0074
39*4882a593Smuzhiyun #define MACB_ELE				0x0078
40*4882a593Smuzhiyun #define MACB_RJA				0x007c
41*4882a593Smuzhiyun #define MACB_USF				0x0080
42*4882a593Smuzhiyun #define MACB_STE				0x0084
43*4882a593Smuzhiyun #define MACB_RLE				0x0088
44*4882a593Smuzhiyun #define MACB_TPF				0x008c
45*4882a593Smuzhiyun #define MACB_HRB				0x0090
46*4882a593Smuzhiyun #define MACB_HRT				0x0094
47*4882a593Smuzhiyun #define MACB_SA1B				0x0098
48*4882a593Smuzhiyun #define MACB_SA1T				0x009c
49*4882a593Smuzhiyun #define MACB_SA2B				0x00a0
50*4882a593Smuzhiyun #define MACB_SA2T				0x00a4
51*4882a593Smuzhiyun #define MACB_SA3B				0x00a8
52*4882a593Smuzhiyun #define MACB_SA3T				0x00ac
53*4882a593Smuzhiyun #define MACB_SA4B				0x00b0
54*4882a593Smuzhiyun #define MACB_SA4T				0x00b4
55*4882a593Smuzhiyun #define MACB_TID				0x00b8
56*4882a593Smuzhiyun #define MACB_TPQ				0x00bc
57*4882a593Smuzhiyun #define MACB_USRIO				0x00c0
58*4882a593Smuzhiyun #define MACB_WOL				0x00c4
59*4882a593Smuzhiyun #define MACB_MID				0x00fc
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun /* GEM specific register offsets */
62*4882a593Smuzhiyun #define GEM_DCFG1				0x0280
63*4882a593Smuzhiyun #define GEM_DCFG6				0x0294
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun #define MACB_MAX_QUEUES				8
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun /* GEM specific multi queues register offset */
68*4882a593Smuzhiyun /* hw_q can be 0~7 */
69*4882a593Smuzhiyun #define GEM_TBQP(hw_q)				(0x0440 + ((hw_q) << 2))
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun /* Bitfields in NCR */
72*4882a593Smuzhiyun #define MACB_LB_OFFSET				0
73*4882a593Smuzhiyun #define MACB_LB_SIZE				1
74*4882a593Smuzhiyun #define MACB_LLB_OFFSET				1
75*4882a593Smuzhiyun #define MACB_LLB_SIZE				1
76*4882a593Smuzhiyun #define MACB_RE_OFFSET				2
77*4882a593Smuzhiyun #define MACB_RE_SIZE				1
78*4882a593Smuzhiyun #define MACB_TE_OFFSET				3
79*4882a593Smuzhiyun #define MACB_TE_SIZE				1
80*4882a593Smuzhiyun #define MACB_MPE_OFFSET				4
81*4882a593Smuzhiyun #define MACB_MPE_SIZE				1
82*4882a593Smuzhiyun #define MACB_CLRSTAT_OFFSET			5
83*4882a593Smuzhiyun #define MACB_CLRSTAT_SIZE			1
84*4882a593Smuzhiyun #define MACB_INCSTAT_OFFSET			6
85*4882a593Smuzhiyun #define MACB_INCSTAT_SIZE			1
86*4882a593Smuzhiyun #define MACB_WESTAT_OFFSET			7
87*4882a593Smuzhiyun #define MACB_WESTAT_SIZE			1
88*4882a593Smuzhiyun #define MACB_BP_OFFSET				8
89*4882a593Smuzhiyun #define MACB_BP_SIZE				1
90*4882a593Smuzhiyun #define MACB_TSTART_OFFSET			9
91*4882a593Smuzhiyun #define MACB_TSTART_SIZE			1
92*4882a593Smuzhiyun #define MACB_THALT_OFFSET			10
93*4882a593Smuzhiyun #define MACB_THALT_SIZE				1
94*4882a593Smuzhiyun #define MACB_NCR_TPF_OFFSET			11
95*4882a593Smuzhiyun #define MACB_NCR_TPF_SIZE			1
96*4882a593Smuzhiyun #define MACB_TZQ_OFFSET				12
97*4882a593Smuzhiyun #define MACB_TZQ_SIZE				1
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun /* Bitfields in NCFGR */
100*4882a593Smuzhiyun #define MACB_SPD_OFFSET				0
101*4882a593Smuzhiyun #define MACB_SPD_SIZE				1
102*4882a593Smuzhiyun #define MACB_FD_OFFSET				1
103*4882a593Smuzhiyun #define MACB_FD_SIZE				1
104*4882a593Smuzhiyun #define MACB_BIT_RATE_OFFSET			2
105*4882a593Smuzhiyun #define MACB_BIT_RATE_SIZE			1
106*4882a593Smuzhiyun #define MACB_JFRAME_OFFSET			3
107*4882a593Smuzhiyun #define MACB_JFRAME_SIZE			1
108*4882a593Smuzhiyun #define MACB_CAF_OFFSET				4
109*4882a593Smuzhiyun #define MACB_CAF_SIZE				1
110*4882a593Smuzhiyun #define MACB_NBC_OFFSET				5
111*4882a593Smuzhiyun #define MACB_NBC_SIZE				1
112*4882a593Smuzhiyun #define MACB_NCFGR_MTI_OFFSET			6
113*4882a593Smuzhiyun #define MACB_NCFGR_MTI_SIZE			1
114*4882a593Smuzhiyun #define MACB_UNI_OFFSET				7
115*4882a593Smuzhiyun #define MACB_UNI_SIZE				1
116*4882a593Smuzhiyun #define MACB_BIG_OFFSET				8
117*4882a593Smuzhiyun #define MACB_BIG_SIZE				1
118*4882a593Smuzhiyun #define MACB_EAE_OFFSET				9
119*4882a593Smuzhiyun #define MACB_EAE_SIZE				1
120*4882a593Smuzhiyun #define MACB_CLK_OFFSET				10
121*4882a593Smuzhiyun #define MACB_CLK_SIZE				2
122*4882a593Smuzhiyun #define MACB_RTY_OFFSET				12
123*4882a593Smuzhiyun #define MACB_RTY_SIZE				1
124*4882a593Smuzhiyun #define MACB_PAE_OFFSET				13
125*4882a593Smuzhiyun #define MACB_PAE_SIZE				1
126*4882a593Smuzhiyun #define MACB_RBOF_OFFSET			14
127*4882a593Smuzhiyun #define MACB_RBOF_SIZE				2
128*4882a593Smuzhiyun #define MACB_RLCE_OFFSET			16
129*4882a593Smuzhiyun #define MACB_RLCE_SIZE				1
130*4882a593Smuzhiyun #define MACB_DRFCS_OFFSET			17
131*4882a593Smuzhiyun #define MACB_DRFCS_SIZE				1
132*4882a593Smuzhiyun #define MACB_EFRHD_OFFSET			18
133*4882a593Smuzhiyun #define MACB_EFRHD_SIZE				1
134*4882a593Smuzhiyun #define MACB_IRXFCS_OFFSET			19
135*4882a593Smuzhiyun #define MACB_IRXFCS_SIZE			1
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun #define GEM_GBE_OFFSET				10
138*4882a593Smuzhiyun #define GEM_GBE_SIZE				1
139*4882a593Smuzhiyun #define GEM_CLK_OFFSET				18
140*4882a593Smuzhiyun #define GEM_CLK_SIZE				3
141*4882a593Smuzhiyun #define GEM_DBW_OFFSET				21
142*4882a593Smuzhiyun #define GEM_DBW_SIZE				2
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun /* Bitfields in NSR */
145*4882a593Smuzhiyun #define MACB_NSR_LINK_OFFSET			0
146*4882a593Smuzhiyun #define MACB_NSR_LINK_SIZE			1
147*4882a593Smuzhiyun #define MACB_MDIO_OFFSET			1
148*4882a593Smuzhiyun #define MACB_MDIO_SIZE				1
149*4882a593Smuzhiyun #define MACB_IDLE_OFFSET			2
150*4882a593Smuzhiyun #define MACB_IDLE_SIZE				1
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun /* Bitfields in UR */
153*4882a593Smuzhiyun #define GEM_RGMII_OFFSET			0
154*4882a593Smuzhiyun #define GEM_RGMII_SIZE				1
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun /* Bitfields in TSR */
157*4882a593Smuzhiyun #define MACB_UBR_OFFSET				0
158*4882a593Smuzhiyun #define MACB_UBR_SIZE				1
159*4882a593Smuzhiyun #define MACB_COL_OFFSET				1
160*4882a593Smuzhiyun #define MACB_COL_SIZE				1
161*4882a593Smuzhiyun #define MACB_TSR_RLE_OFFSET			2
162*4882a593Smuzhiyun #define MACB_TSR_RLE_SIZE			1
163*4882a593Smuzhiyun #define MACB_TGO_OFFSET				3
164*4882a593Smuzhiyun #define MACB_TGO_SIZE				1
165*4882a593Smuzhiyun #define MACB_BEX_OFFSET				4
166*4882a593Smuzhiyun #define MACB_BEX_SIZE				1
167*4882a593Smuzhiyun #define MACB_COMP_OFFSET			5
168*4882a593Smuzhiyun #define MACB_COMP_SIZE				1
169*4882a593Smuzhiyun #define MACB_UND_OFFSET				6
170*4882a593Smuzhiyun #define MACB_UND_SIZE				1
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun /* Bitfields in RSR */
173*4882a593Smuzhiyun #define MACB_BNA_OFFSET				0
174*4882a593Smuzhiyun #define MACB_BNA_SIZE				1
175*4882a593Smuzhiyun #define MACB_REC_OFFSET				1
176*4882a593Smuzhiyun #define MACB_REC_SIZE				1
177*4882a593Smuzhiyun #define MACB_OVR_OFFSET				2
178*4882a593Smuzhiyun #define MACB_OVR_SIZE				1
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun /* Bitfields in ISR/IER/IDR/IMR */
181*4882a593Smuzhiyun #define MACB_MFD_OFFSET				0
182*4882a593Smuzhiyun #define MACB_MFD_SIZE				1
183*4882a593Smuzhiyun #define MACB_RCOMP_OFFSET			1
184*4882a593Smuzhiyun #define MACB_RCOMP_SIZE				1
185*4882a593Smuzhiyun #define MACB_RXUBR_OFFSET			2
186*4882a593Smuzhiyun #define MACB_RXUBR_SIZE				1
187*4882a593Smuzhiyun #define MACB_TXUBR_OFFSET			3
188*4882a593Smuzhiyun #define MACB_TXUBR_SIZE				1
189*4882a593Smuzhiyun #define MACB_ISR_TUND_OFFSET			4
190*4882a593Smuzhiyun #define MACB_ISR_TUND_SIZE			1
191*4882a593Smuzhiyun #define MACB_ISR_RLE_OFFSET			5
192*4882a593Smuzhiyun #define MACB_ISR_RLE_SIZE			1
193*4882a593Smuzhiyun #define MACB_TXERR_OFFSET			6
194*4882a593Smuzhiyun #define MACB_TXERR_SIZE				1
195*4882a593Smuzhiyun #define MACB_TCOMP_OFFSET			7
196*4882a593Smuzhiyun #define MACB_TCOMP_SIZE				1
197*4882a593Smuzhiyun #define MACB_ISR_LINK_OFFSET			9
198*4882a593Smuzhiyun #define MACB_ISR_LINK_SIZE			1
199*4882a593Smuzhiyun #define MACB_ISR_ROVR_OFFSET			10
200*4882a593Smuzhiyun #define MACB_ISR_ROVR_SIZE			1
201*4882a593Smuzhiyun #define MACB_HRESP_OFFSET			11
202*4882a593Smuzhiyun #define MACB_HRESP_SIZE				1
203*4882a593Smuzhiyun #define MACB_PFR_OFFSET				12
204*4882a593Smuzhiyun #define MACB_PFR_SIZE				1
205*4882a593Smuzhiyun #define MACB_PTZ_OFFSET				13
206*4882a593Smuzhiyun #define MACB_PTZ_SIZE				1
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun /* Bitfields in MAN */
209*4882a593Smuzhiyun #define MACB_DATA_OFFSET			0
210*4882a593Smuzhiyun #define MACB_DATA_SIZE				16
211*4882a593Smuzhiyun #define MACB_CODE_OFFSET			16
212*4882a593Smuzhiyun #define MACB_CODE_SIZE				2
213*4882a593Smuzhiyun #define MACB_REGA_OFFSET			18
214*4882a593Smuzhiyun #define MACB_REGA_SIZE				5
215*4882a593Smuzhiyun #define MACB_PHYA_OFFSET			23
216*4882a593Smuzhiyun #define MACB_PHYA_SIZE				5
217*4882a593Smuzhiyun #define MACB_RW_OFFSET				28
218*4882a593Smuzhiyun #define MACB_RW_SIZE				2
219*4882a593Smuzhiyun #define MACB_SOF_OFFSET				30
220*4882a593Smuzhiyun #define MACB_SOF_SIZE				2
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun /* Bitfields in USRIO */
223*4882a593Smuzhiyun #define MACB_MII_OFFSET				0
224*4882a593Smuzhiyun #define MACB_MII_SIZE				1
225*4882a593Smuzhiyun #define MACB_EAM_OFFSET				1
226*4882a593Smuzhiyun #define MACB_EAM_SIZE				1
227*4882a593Smuzhiyun #define MACB_TX_PAUSE_OFFSET			2
228*4882a593Smuzhiyun #define MACB_TX_PAUSE_SIZE			1
229*4882a593Smuzhiyun #define MACB_TX_PAUSE_ZERO_OFFSET		3
230*4882a593Smuzhiyun #define MACB_TX_PAUSE_ZERO_SIZE			1
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun /* Bitfields in USRIO (AT91) */
233*4882a593Smuzhiyun #define MACB_RMII_OFFSET			0
234*4882a593Smuzhiyun #define MACB_RMII_SIZE				1
235*4882a593Smuzhiyun #define MACB_CLKEN_OFFSET			1
236*4882a593Smuzhiyun #define MACB_CLKEN_SIZE				1
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun /* Bitfields in WOL */
239*4882a593Smuzhiyun #define MACB_IP_OFFSET				0
240*4882a593Smuzhiyun #define MACB_IP_SIZE				16
241*4882a593Smuzhiyun #define MACB_MAG_OFFSET				16
242*4882a593Smuzhiyun #define MACB_MAG_SIZE				1
243*4882a593Smuzhiyun #define MACB_ARP_OFFSET				17
244*4882a593Smuzhiyun #define MACB_ARP_SIZE				1
245*4882a593Smuzhiyun #define MACB_SA1_OFFSET				18
246*4882a593Smuzhiyun #define MACB_SA1_SIZE				1
247*4882a593Smuzhiyun #define MACB_WOL_MTI_OFFSET			19
248*4882a593Smuzhiyun #define MACB_WOL_MTI_SIZE			1
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun /* Bitfields in MID */
251*4882a593Smuzhiyun #define MACB_IDNUM_OFFSET			16
252*4882a593Smuzhiyun #define MACB_IDNUM_SIZE				16
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun /* Bitfields in DCFG1 */
255*4882a593Smuzhiyun #define GEM_DBWDEF_OFFSET			25
256*4882a593Smuzhiyun #define GEM_DBWDEF_SIZE				3
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun /* constants for data bus width */
259*4882a593Smuzhiyun #define GEM_DBW32				0
260*4882a593Smuzhiyun #define GEM_DBW64				1
261*4882a593Smuzhiyun #define GEM_DBW128				2
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun /* Constants for CLK */
264*4882a593Smuzhiyun #define MACB_CLK_DIV8				0
265*4882a593Smuzhiyun #define MACB_CLK_DIV16				1
266*4882a593Smuzhiyun #define MACB_CLK_DIV32				2
267*4882a593Smuzhiyun #define MACB_CLK_DIV64				3
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun /* GEM specific constants for CLK */
270*4882a593Smuzhiyun #define GEM_CLK_DIV8				0
271*4882a593Smuzhiyun #define GEM_CLK_DIV16				1
272*4882a593Smuzhiyun #define GEM_CLK_DIV32				2
273*4882a593Smuzhiyun #define GEM_CLK_DIV48				3
274*4882a593Smuzhiyun #define GEM_CLK_DIV64				4
275*4882a593Smuzhiyun #define GEM_CLK_DIV96				5
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun /* Constants for MAN register */
278*4882a593Smuzhiyun #define MACB_MAN_SOF				1
279*4882a593Smuzhiyun #define MACB_MAN_WRITE				1
280*4882a593Smuzhiyun #define MACB_MAN_READ				2
281*4882a593Smuzhiyun #define MACB_MAN_CODE				2
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun /* Bit manipulation macros */
284*4882a593Smuzhiyun #define MACB_BIT(name)					\
285*4882a593Smuzhiyun 	(1 << MACB_##name##_OFFSET)
286*4882a593Smuzhiyun #define MACB_BF(name, value)				\
287*4882a593Smuzhiyun 	(((value) & ((1 << MACB_##name##_SIZE) - 1))	\
288*4882a593Smuzhiyun 	 << MACB_##name##_OFFSET)
289*4882a593Smuzhiyun #define MACB_BFEXT(name, value)\
290*4882a593Smuzhiyun 	(((value) >> MACB_##name##_OFFSET)		\
291*4882a593Smuzhiyun 	 & ((1 << MACB_##name##_SIZE) - 1))
292*4882a593Smuzhiyun #define MACB_BFINS(name, value, old)			\
293*4882a593Smuzhiyun 	(((old) & ~(((1 << MACB_##name##_SIZE) - 1)	\
294*4882a593Smuzhiyun 		    << MACB_##name##_OFFSET))		\
295*4882a593Smuzhiyun 	 | MACB_BF(name, value))
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun #define GEM_BIT(name)					\
298*4882a593Smuzhiyun 	(1 << GEM_##name##_OFFSET)
299*4882a593Smuzhiyun #define GEM_BF(name, value)				\
300*4882a593Smuzhiyun 	(((value) & ((1 << GEM_##name##_SIZE) - 1))	\
301*4882a593Smuzhiyun 	 << GEM_##name##_OFFSET)
302*4882a593Smuzhiyun #define GEM_BFEXT(name, value)\
303*4882a593Smuzhiyun 	(((value) >> GEM_##name##_OFFSET)		\
304*4882a593Smuzhiyun 	 & ((1 << GEM_##name##_SIZE) - 1))
305*4882a593Smuzhiyun #define GEM_BFINS(name, value, old)			\
306*4882a593Smuzhiyun 	(((old) & ~(((1 << GEM_##name##_SIZE) - 1)	\
307*4882a593Smuzhiyun 		    << GEM_##name##_OFFSET))		\
308*4882a593Smuzhiyun 	 | GEM_BF(name, value))
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun /* Register access macros */
311*4882a593Smuzhiyun #define macb_readl(port, reg)				\
312*4882a593Smuzhiyun 	readl((port)->regs + MACB_##reg)
313*4882a593Smuzhiyun #define macb_writel(port, reg, value)			\
314*4882a593Smuzhiyun 	writel((value), (port)->regs + MACB_##reg)
315*4882a593Smuzhiyun #define gem_readl(port, reg)				\
316*4882a593Smuzhiyun 	readl((port)->regs + GEM_##reg)
317*4882a593Smuzhiyun #define gem_writel(port, reg, value)			\
318*4882a593Smuzhiyun 	writel((value), (port)->regs + GEM_##reg)
319*4882a593Smuzhiyun #define gem_writel_queue_TBQP(port, value, queue_num)	\
320*4882a593Smuzhiyun 	writel((value), (port)->regs + GEM_TBQP(queue_num))
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun #endif /* __DRIVERS_MACB_H__ */
323