1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2015 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun #include <common.h>
7*4882a593Smuzhiyun #include <phy.h>
8*4882a593Smuzhiyun #include <fsl-mc/ldpaa_wriop.h>
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <asm/arch/fsl_serdes.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun u32 dpmac_to_devdisr[] = {
13*4882a593Smuzhiyun [WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
14*4882a593Smuzhiyun [WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2,
15*4882a593Smuzhiyun [WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3,
16*4882a593Smuzhiyun [WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4,
17*4882a593Smuzhiyun [WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5,
18*4882a593Smuzhiyun [WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6,
19*4882a593Smuzhiyun [WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7,
20*4882a593Smuzhiyun [WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8,
21*4882a593Smuzhiyun [WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9,
22*4882a593Smuzhiyun [WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10,
23*4882a593Smuzhiyun [WRIOP1_DPMAC11] = FSL_CHASSIS3_DEVDISR2_DPMAC11,
24*4882a593Smuzhiyun [WRIOP1_DPMAC12] = FSL_CHASSIS3_DEVDISR2_DPMAC12,
25*4882a593Smuzhiyun [WRIOP1_DPMAC13] = FSL_CHASSIS3_DEVDISR2_DPMAC13,
26*4882a593Smuzhiyun [WRIOP1_DPMAC14] = FSL_CHASSIS3_DEVDISR2_DPMAC14,
27*4882a593Smuzhiyun [WRIOP1_DPMAC15] = FSL_CHASSIS3_DEVDISR2_DPMAC15,
28*4882a593Smuzhiyun [WRIOP1_DPMAC16] = FSL_CHASSIS3_DEVDISR2_DPMAC16,
29*4882a593Smuzhiyun [WRIOP1_DPMAC17] = FSL_CHASSIS3_DEVDISR2_DPMAC17,
30*4882a593Smuzhiyun [WRIOP1_DPMAC18] = FSL_CHASSIS3_DEVDISR2_DPMAC18,
31*4882a593Smuzhiyun [WRIOP1_DPMAC19] = FSL_CHASSIS3_DEVDISR2_DPMAC19,
32*4882a593Smuzhiyun [WRIOP1_DPMAC20] = FSL_CHASSIS3_DEVDISR2_DPMAC20,
33*4882a593Smuzhiyun [WRIOP1_DPMAC21] = FSL_CHASSIS3_DEVDISR2_DPMAC21,
34*4882a593Smuzhiyun [WRIOP1_DPMAC22] = FSL_CHASSIS3_DEVDISR2_DPMAC22,
35*4882a593Smuzhiyun [WRIOP1_DPMAC23] = FSL_CHASSIS3_DEVDISR2_DPMAC23,
36*4882a593Smuzhiyun [WRIOP1_DPMAC24] = FSL_CHASSIS3_DEVDISR2_DPMAC24,
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
is_device_disabled(int dpmac_id)39*4882a593Smuzhiyun static int is_device_disabled(int dpmac_id)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
42*4882a593Smuzhiyun u32 devdisr2 = in_le32(&gur->devdisr2);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun return dpmac_to_devdisr[dpmac_id] & devdisr2;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
wriop_dpmac_disable(int dpmac_id)47*4882a593Smuzhiyun void wriop_dpmac_disable(int dpmac_id)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
wriop_dpmac_enable(int dpmac_id)54*4882a593Smuzhiyun void wriop_dpmac_enable(int dpmac_id)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
wriop_dpmac_enet_if(int dpmac_id,int lane_prtcl)61*4882a593Smuzhiyun phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun enum srds_prtcl;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun if (is_device_disabled(dpmac_id + 1))
66*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII16)
69*4882a593Smuzhiyun return PHY_INTERFACE_MODE_SGMII;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
72*4882a593Smuzhiyun return PHY_INTERFACE_MODE_XGMII;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun if (lane_prtcl >= XAUI1 && lane_prtcl <= XAUI2)
75*4882a593Smuzhiyun return PHY_INTERFACE_MODE_XGMII;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_D)
78*4882a593Smuzhiyun return PHY_INTERFACE_MODE_QSGMII;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
wriop_init_dpmac_qsgmii(int sd,int lane_prtcl)83*4882a593Smuzhiyun void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun switch (lane_prtcl) {
86*4882a593Smuzhiyun case QSGMII_A:
87*4882a593Smuzhiyun wriop_init_dpmac(sd, 5, (int)lane_prtcl);
88*4882a593Smuzhiyun wriop_init_dpmac(sd, 6, (int)lane_prtcl);
89*4882a593Smuzhiyun wriop_init_dpmac(sd, 7, (int)lane_prtcl);
90*4882a593Smuzhiyun wriop_init_dpmac(sd, 8, (int)lane_prtcl);
91*4882a593Smuzhiyun break;
92*4882a593Smuzhiyun case QSGMII_B:
93*4882a593Smuzhiyun wriop_init_dpmac(sd, 1, (int)lane_prtcl);
94*4882a593Smuzhiyun wriop_init_dpmac(sd, 2, (int)lane_prtcl);
95*4882a593Smuzhiyun wriop_init_dpmac(sd, 3, (int)lane_prtcl);
96*4882a593Smuzhiyun wriop_init_dpmac(sd, 4, (int)lane_prtcl);
97*4882a593Smuzhiyun break;
98*4882a593Smuzhiyun case QSGMII_C:
99*4882a593Smuzhiyun wriop_init_dpmac(sd, 13, (int)lane_prtcl);
100*4882a593Smuzhiyun wriop_init_dpmac(sd, 14, (int)lane_prtcl);
101*4882a593Smuzhiyun wriop_init_dpmac(sd, 15, (int)lane_prtcl);
102*4882a593Smuzhiyun wriop_init_dpmac(sd, 16, (int)lane_prtcl);
103*4882a593Smuzhiyun break;
104*4882a593Smuzhiyun case QSGMII_D:
105*4882a593Smuzhiyun wriop_init_dpmac(sd, 9, (int)lane_prtcl);
106*4882a593Smuzhiyun wriop_init_dpmac(sd, 10, (int)lane_prtcl);
107*4882a593Smuzhiyun wriop_init_dpmac(sd, 11, (int)lane_prtcl);
108*4882a593Smuzhiyun wriop_init_dpmac(sd, 12, (int)lane_prtcl);
109*4882a593Smuzhiyun break;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun }
112