1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2014 Freescale Semiconductor 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __LDPAA_ETH_H 8*4882a593Smuzhiyun #define __LDPAA_ETH_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/netdevice.h> 11*4882a593Smuzhiyun #include <fsl-mc/fsl_mc.h> 12*4882a593Smuzhiyun #include <fsl-mc/fsl_dpaa_fd.h> 13*4882a593Smuzhiyun #include <fsl-mc/fsl_dprc.h> 14*4882a593Smuzhiyun #include <fsl-mc/fsl_dpni.h> 15*4882a593Smuzhiyun #include <fsl-mc/fsl_dpbp.h> 16*4882a593Smuzhiyun #include <fsl-mc/fsl_dpio.h> 17*4882a593Smuzhiyun #include <fsl-mc/fsl_qbman_portal.h> 18*4882a593Smuzhiyun #include <fsl-mc/fsl_mc_private.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun enum ldpaa_eth_type { 22*4882a593Smuzhiyun LDPAA_ETH_1G_E, 23*4882a593Smuzhiyun LDPAA_ETH_10G_E, 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Arbitrary values for now, but we'll need to tune */ 27*4882a593Smuzhiyun #define LDPAA_ETH_NUM_BUFS (7 * 7) 28*4882a593Smuzhiyun #define LDPAA_ETH_REFILL_THRESH (LDPAA_ETH_NUM_BUFS/2) 29*4882a593Smuzhiyun #define LDPAA_ETH_RX_BUFFER_SIZE 2048 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* Hardware requires alignment for buffer address and length: 256-byte 32*4882a593Smuzhiyun * for ingress, 64-byte for egress. Using 256 for both. 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun #define LDPAA_ETH_BUF_ALIGN 256 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* So far we're only accomodating a skb backpointer in the frame's 37*4882a593Smuzhiyun * software annotation, but the hardware options are either 0 or 64. 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun #define LDPAA_ETH_SWA_SIZE 64 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Annotation valid bits in FD FRC */ 42*4882a593Smuzhiyun #define LDPAA_FD_FRC_FASV 0x8000 43*4882a593Smuzhiyun #define LDPAA_FD_FRC_FAEADV 0x4000 44*4882a593Smuzhiyun #define LDPAA_FD_FRC_FAPRV 0x2000 45*4882a593Smuzhiyun #define LDPAA_FD_FRC_FAIADV 0x1000 46*4882a593Smuzhiyun #define LDPAA_FD_FRC_FASWOV 0x0800 47*4882a593Smuzhiyun #define LDPAA_FD_FRC_FAICFDV 0x0400 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* Annotation bits in FD CTRL */ 50*4882a593Smuzhiyun #define LDPAA_FD_CTRL_ASAL 0x00020000 /* ASAL = 128 */ 51*4882a593Smuzhiyun #define LDPAA_FD_CTRL_PTA 0x00800000 52*4882a593Smuzhiyun #define LDPAA_FD_CTRL_PTV1 0x00400000 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* TODO: we may want to move this and other WRIOP related defines 55*4882a593Smuzhiyun * to a separate header 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun /* Frame annotation status */ 58*4882a593Smuzhiyun struct ldpaa_fas { 59*4882a593Smuzhiyun u8 reserved; 60*4882a593Smuzhiyun u8 ppid; 61*4882a593Smuzhiyun __le16 ifpid; 62*4882a593Smuzhiyun __le32 status; 63*4882a593Smuzhiyun } __packed; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* Debug frame, otherwise supposed to be discarded */ 66*4882a593Smuzhiyun #define LDPAA_ETH_FAS_DISC 0x80000000 67*4882a593Smuzhiyun /* MACSEC frame */ 68*4882a593Smuzhiyun #define LDPAA_ETH_FAS_MS 0x40000000 69*4882a593Smuzhiyun #define LDPAA_ETH_FAS_PTP 0x08000000 70*4882a593Smuzhiyun /* Ethernet multicast frame */ 71*4882a593Smuzhiyun #define LDPAA_ETH_FAS_MC 0x04000000 72*4882a593Smuzhiyun /* Ethernet broadcast frame */ 73*4882a593Smuzhiyun #define LDPAA_ETH_FAS_BC 0x02000000 74*4882a593Smuzhiyun #define LDPAA_ETH_FAS_KSE 0x00040000 75*4882a593Smuzhiyun #define LDPAA_ETH_FAS_EOFHE 0x00020000 76*4882a593Smuzhiyun #define LDPAA_ETH_FAS_MNLE 0x00010000 77*4882a593Smuzhiyun #define LDPAA_ETH_FAS_TIDE 0x00008000 78*4882a593Smuzhiyun #define LDPAA_ETH_FAS_PIEE 0x00004000 79*4882a593Smuzhiyun /* Frame length error */ 80*4882a593Smuzhiyun #define LDPAA_ETH_FAS_FLE 0x00002000 81*4882a593Smuzhiyun /* Frame physical error; our favourite pastime */ 82*4882a593Smuzhiyun #define LDPAA_ETH_FAS_FPE 0x00001000 83*4882a593Smuzhiyun #define LDPAA_ETH_FAS_PTE 0x00000080 84*4882a593Smuzhiyun #define LDPAA_ETH_FAS_ISP 0x00000040 85*4882a593Smuzhiyun #define LDPAA_ETH_FAS_PHE 0x00000020 86*4882a593Smuzhiyun #define LDPAA_ETH_FAS_BLE 0x00000010 87*4882a593Smuzhiyun /* L3 csum validation performed */ 88*4882a593Smuzhiyun #define LDPAA_ETH_FAS_L3CV 0x00000008 89*4882a593Smuzhiyun /* L3 csum error */ 90*4882a593Smuzhiyun #define LDPAA_ETH_FAS_L3CE 0x00000004 91*4882a593Smuzhiyun /* L4 csum validation performed */ 92*4882a593Smuzhiyun #define LDPAA_ETH_FAS_L4CV 0x00000002 93*4882a593Smuzhiyun /* L4 csum error */ 94*4882a593Smuzhiyun #define LDPAA_ETH_FAS_L4CE 0x00000001 95*4882a593Smuzhiyun /* These bits always signal errors */ 96*4882a593Smuzhiyun #define LDPAA_ETH_RX_ERR_MASK (LDPAA_ETH_FAS_DISC | \ 97*4882a593Smuzhiyun LDPAA_ETH_FAS_KSE | \ 98*4882a593Smuzhiyun LDPAA_ETH_FAS_EOFHE | \ 99*4882a593Smuzhiyun LDPAA_ETH_FAS_MNLE | \ 100*4882a593Smuzhiyun LDPAA_ETH_FAS_TIDE | \ 101*4882a593Smuzhiyun LDPAA_ETH_FAS_PIEE | \ 102*4882a593Smuzhiyun LDPAA_ETH_FAS_FLE | \ 103*4882a593Smuzhiyun LDPAA_ETH_FAS_FPE | \ 104*4882a593Smuzhiyun LDPAA_ETH_FAS_PTE | \ 105*4882a593Smuzhiyun LDPAA_ETH_FAS_ISP | \ 106*4882a593Smuzhiyun LDPAA_ETH_FAS_PHE | \ 107*4882a593Smuzhiyun LDPAA_ETH_FAS_BLE | \ 108*4882a593Smuzhiyun LDPAA_ETH_FAS_L3CE | \ 109*4882a593Smuzhiyun LDPAA_ETH_FAS_L4CE) 110*4882a593Smuzhiyun /* Unsupported features in the ingress */ 111*4882a593Smuzhiyun #define LDPAA_ETH_RX_UNSUPP_MASK LDPAA_ETH_FAS_MS 112*4882a593Smuzhiyun /* TODO trim down the bitmask; not all of them apply to Tx-confirm */ 113*4882a593Smuzhiyun #define LDPAA_ETH_TXCONF_ERR_MASK (LDPAA_ETH_FAS_KSE | \ 114*4882a593Smuzhiyun LDPAA_ETH_FAS_EOFHE | \ 115*4882a593Smuzhiyun LDPAA_ETH_FAS_MNLE | \ 116*4882a593Smuzhiyun LDPAA_ETH_FAS_TIDE) 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun struct ldpaa_eth_priv { 119*4882a593Smuzhiyun struct eth_device *net_dev; 120*4882a593Smuzhiyun int dpmac_id; 121*4882a593Smuzhiyun uint16_t dpmac_handle; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun uint16_t tx_data_offset; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun uint32_t rx_dflt_fqid; 126*4882a593Smuzhiyun uint16_t tx_qdid; 127*4882a593Smuzhiyun uint16_t tx_flow_id; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun enum ldpaa_eth_type type; /* 1G or 10G ethernet */ 130*4882a593Smuzhiyun struct phy_device *phydev; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun struct dprc_endpoint dpmac_endpoint; 134*4882a593Smuzhiyun struct dprc_endpoint dpni_endpoint; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun extern struct fsl_mc_io *dflt_mc_io; 137*4882a593Smuzhiyun extern struct fsl_dpbp_obj *dflt_dpbp; 138*4882a593Smuzhiyun extern struct fsl_dpio_obj *dflt_dpio; 139*4882a593Smuzhiyun extern struct fsl_dpni_obj *dflt_dpni; 140*4882a593Smuzhiyun extern uint16_t dflt_dprc_handle; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun static void ldpaa_dpbp_drain_cnt(int count); 143*4882a593Smuzhiyun static void ldpaa_dpbp_drain(void); 144*4882a593Smuzhiyun static int ldpaa_dpbp_seed(uint16_t bpid); 145*4882a593Smuzhiyun static void ldpaa_dpbp_free(void); 146*4882a593Smuzhiyun static int ldpaa_dpni_setup(struct ldpaa_eth_priv *priv); 147*4882a593Smuzhiyun static int ldpaa_dpbp_setup(void); 148*4882a593Smuzhiyun static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv); 149*4882a593Smuzhiyun static int ldpaa_dpmac_setup(struct ldpaa_eth_priv *priv); 150*4882a593Smuzhiyun static int ldpaa_dpmac_bind(struct ldpaa_eth_priv *priv); 151*4882a593Smuzhiyun #endif /* __LDPAA_H */ 152