1 /*
2 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 *
6 * Rockchip GMAC ethernet IP driver for U-Boot
7 */
8
9 #include <common.h>
10 #include <dm.h>
11 #include <clk.h>
12 #include <misc.h>
13 #include <phy.h>
14 #include <reset.h>
15 #include <syscon.h>
16 #include <asm/io.h>
17 #include <asm/arch/periph.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/hardware.h>
20 #ifdef CONFIG_DWC_ETH_QOS
21 #include <asm/arch/grf_rk3528.h>
22 #include <asm/arch/grf_rk3562.h>
23 #include <asm/arch/ioc_rk3562.h>
24 #include <asm/arch/grf_rk3568.h>
25 #include <asm/arch/grf_rk3588.h>
26 #include <asm/arch/grf_rv1106.h>
27 #include <asm/arch/grf_rv1126.h>
28 #include "dwc_eth_qos.h"
29 #else
30 #include <asm/arch/grf_px30.h>
31 #include <asm/arch/grf_rk1808.h>
32 #include <asm/arch/grf_rk322x.h>
33 #include <asm/arch/grf_rk3288.h>
34 #include <asm/arch/grf_rk3308.h>
35 #include <asm/arch/grf_rk3328.h>
36 #include <asm/arch/grf_rk3368.h>
37 #include <asm/arch/grf_rk3399.h>
38 #include <asm/arch/grf_rv1108.h>
39 #include "designware.h"
40 #include <dt-bindings/clock/rk3288-cru.h>
41 #endif
42 #include <dm/pinctrl.h>
43 #include <dm/of_access.h>
44
45 DECLARE_GLOBAL_DATA_PTR;
46
47 struct rockchip_eth_dev {
48 #ifdef CONFIG_DWC_ETH_QOS
49 struct eqos_priv eqos;
50 #else
51 struct dw_eth_dev dw;
52 #endif
53 int phy_interface;
54 };
55
56 /*
57 * Platform data for the gmac
58 *
59 * dw_eth_pdata: Required platform data for designware driver (must be first)
60 */
61 struct gmac_rockchip_platdata {
62 #ifndef CONFIG_DWC_ETH_QOS
63 struct dw_eth_pdata dw_eth_pdata;
64 #else
65 struct eth_pdata eth_pdata;
66 #endif
67 struct reset_ctl phy_reset;
68 bool integrated_phy;
69 bool clock_input;
70 int phy_interface;
71 int tx_delay;
72 int rx_delay;
73 int bus_id;
74 };
75
76 struct rk_gmac_ops {
77 #ifdef CONFIG_DWC_ETH_QOS
78 const struct eqos_config config;
79 #endif
80 int (*fix_mac_speed)(struct gmac_rockchip_platdata *pdata,
81 struct rockchip_eth_dev *dev);
82 void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
83 void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
84 void (*set_clock_selection)(struct gmac_rockchip_platdata *pdata);
85 void (*integrated_phy_powerup)(struct gmac_rockchip_platdata *pdata);
86 };
87
88 #ifdef CONFIG_DWC_ETH_QOS
89 static const struct eqos_config eqos_rockchip_config = {
90 .reg_access_always_ok = false,
91 .mdio_wait = 10000,
92 .swr_wait = 200,
93 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED,
94 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_100_150,
95 .ops = &eqos_rockchip_ops,
96 };
97 #endif
98
gmac_set_rgmii(struct udevice * dev,u32 tx_delay,u32 rx_delay)99 void gmac_set_rgmii(struct udevice *dev, u32 tx_delay, u32 rx_delay)
100 {
101 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
102 struct rk_gmac_ops *ops =
103 (struct rk_gmac_ops *)dev_get_driver_data(dev);
104
105 pdata->tx_delay = tx_delay;
106 pdata->rx_delay = rx_delay;
107
108 ops->set_to_rgmii(pdata);
109 }
110
gmac_rockchip_ofdata_to_platdata(struct udevice * dev)111 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
112 {
113 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
114 struct ofnode_phandle_args args;
115 struct udevice *phydev;
116 const char *string;
117 int ret;
118
119 string = dev_read_string(dev, "clock_in_out");
120 if (!strcmp(string, "input"))
121 pdata->clock_input = true;
122 else
123 pdata->clock_input = false;
124
125 /* If phy-handle property is passed from DT, use it as the PHY */
126 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &args);
127 if (ret) {
128 debug("Cannot get phy phandle: ret=%d\n", ret);
129 pdata->integrated_phy = dev_read_bool(dev, "phy-is-integrated");
130 } else {
131 debug("Found phy-handle subnode\n");
132 pdata->integrated_phy = ofnode_read_bool(args.node,
133 "phy-is-integrated");
134 }
135
136 if (pdata->integrated_phy) {
137 ret = reset_get_by_name(dev, "mac-phy", &pdata->phy_reset);
138 if (ret) {
139 ret = uclass_get_device_by_ofnode(UCLASS_ETH_PHY, args.node, &phydev);
140 if (ret) {
141 debug("Get phydev by ofnode failed: err=%d\n", ret);
142 return ret;
143 }
144
145 ret = reset_get_by_index(phydev, 0, &pdata->phy_reset);
146 if (ret) {
147 debug("No PHY reset control found: ret=%d\n", ret);
148 return ret;
149 }
150 }
151 }
152
153 /* Check the new naming-style first... */
154 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT);
155 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT);
156
157 /* ... and fall back to the old naming style or default, if necessary */
158 if (pdata->tx_delay == -ENOENT)
159 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30);
160 if (pdata->rx_delay == -ENOENT)
161 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10);
162
163 #ifdef CONFIG_DWC_ETH_QOS
164 return 0;
165 #else
166 return designware_eth_ofdata_to_platdata(dev);
167 #endif
168 }
169
170 #ifndef CONFIG_DWC_ETH_QOS
px30_gmac_fix_mac_speed(struct gmac_rockchip_platdata * pdata,struct rockchip_eth_dev * dev)171 static int px30_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata,
172 struct rockchip_eth_dev *dev)
173 {
174 struct dw_eth_dev *priv = &dev->dw;
175 struct px30_grf *grf;
176 struct clk clk_speed;
177 int speed, ret;
178 enum {
179 PX30_GMAC_SPEED_SHIFT = 0x2,
180 PX30_GMAC_SPEED_MASK = BIT(2),
181 PX30_GMAC_SPEED_10M = 0,
182 PX30_GMAC_SPEED_100M = BIT(2),
183 };
184
185 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed",
186 &clk_speed);
187 if (ret)
188 return ret;
189
190 switch (priv->phydev->speed) {
191 case 10:
192 speed = PX30_GMAC_SPEED_10M;
193 ret = clk_set_rate(&clk_speed, 2500000);
194 if (ret)
195 return ret;
196 break;
197 case 100:
198 speed = PX30_GMAC_SPEED_100M;
199 ret = clk_set_rate(&clk_speed, 25000000);
200 if (ret)
201 return ret;
202 break;
203 default:
204 debug("Unknown phy speed: %d\n", priv->phydev->speed);
205 return -EINVAL;
206 }
207
208 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
209 rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed);
210
211 return 0;
212 }
213
rk1808_gmac_fix_mac_speed(struct gmac_rockchip_platdata * pdata,struct rockchip_eth_dev * dev)214 static int rk1808_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata,
215 struct rockchip_eth_dev *dev)
216 {
217 struct dw_eth_dev *priv = &dev->dw;
218 struct clk clk_speed;
219 int ret;
220
221 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed",
222 &clk_speed);
223 if (ret)
224 return ret;
225
226 switch (priv->phydev->speed) {
227 case 10:
228 ret = clk_set_rate(&clk_speed, 2500000);
229 if (ret)
230 return ret;
231 break;
232 case 100:
233 ret = clk_set_rate(&clk_speed, 25000000);
234 if (ret)
235 return ret;
236 break;
237 case 1000:
238 ret = clk_set_rate(&clk_speed, 125000000);
239 if (ret)
240 return ret;
241 break;
242 default:
243 debug("Unknown phy speed: %d\n", priv->phydev->speed);
244 return -EINVAL;
245 }
246
247 return 0;
248 }
249
rk3228_gmac_fix_mac_speed(struct gmac_rockchip_platdata * pdata,struct rockchip_eth_dev * dev)250 static int rk3228_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata,
251 struct rockchip_eth_dev *dev)
252 {
253 struct dw_eth_dev *priv = &dev->dw;
254 struct rk322x_grf *grf;
255 int clk;
256 enum {
257 RK3228_GMAC_CLK_SEL_SHIFT = 8,
258 RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8),
259 RK3228_GMAC_CLK_SEL_125M = 0 << 8,
260 RK3228_GMAC_CLK_SEL_25M = 3 << 8,
261 RK3228_GMAC_CLK_SEL_2_5M = 2 << 8,
262
263 RK3228_GMAC_RMII_CLK_MASK = BIT(7),
264 RK3228_GMAC_RMII_CLK_2_5M = 0,
265 RK3228_GMAC_RMII_CLK_25M = BIT(7),
266
267 RK3228_GMAC_RMII_SPEED_MASK = BIT(2),
268 RK3228_GMAC_RMII_SPEED_10 = 0,
269 RK3228_GMAC_RMII_SPEED_100 = BIT(2),
270 };
271
272 switch (priv->phydev->speed) {
273 case 10:
274 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ?
275 (RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_RMII_SPEED_10) :
276 RK3228_GMAC_CLK_SEL_2_5M;
277 break;
278 case 100:
279 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ?
280 (RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_RMII_SPEED_100) :
281 RK3228_GMAC_CLK_SEL_25M;
282 break;
283 case 1000:
284 clk = RK3228_GMAC_CLK_SEL_125M;
285 break;
286 default:
287 debug("Unknown phy speed: %d\n", priv->phydev->speed);
288 return -EINVAL;
289 }
290
291 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
292 rk_clrsetreg(&grf->mac_con[1],
293 RK3228_GMAC_CLK_SEL_MASK |
294 RK3228_GMAC_RMII_CLK_MASK |
295 RK3228_GMAC_RMII_SPEED_MASK,
296 clk);
297
298 return 0;
299 }
300
rk3288_gmac_fix_mac_speed(struct gmac_rockchip_platdata * pdata,struct rockchip_eth_dev * dev)301 static int rk3288_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata,
302 struct rockchip_eth_dev *dev)
303 {
304 struct dw_eth_dev *priv = &dev->dw;
305 struct rk3288_grf *grf;
306 int clk;
307
308 switch (priv->phydev->speed) {
309 case 10:
310 clk = RK3288_GMAC_CLK_SEL_2_5M;
311 break;
312 case 100:
313 clk = RK3288_GMAC_CLK_SEL_25M;
314 break;
315 case 1000:
316 clk = RK3288_GMAC_CLK_SEL_125M;
317 break;
318 default:
319 debug("Unknown phy speed: %d\n", priv->phydev->speed);
320 return -EINVAL;
321 }
322
323 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
324 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk);
325
326 return 0;
327 }
328
rk3308_gmac_fix_mac_speed(struct gmac_rockchip_platdata * pdata,struct rockchip_eth_dev * dev)329 static int rk3308_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata,
330 struct rockchip_eth_dev *dev)
331 {
332 struct dw_eth_dev *priv = &dev->dw;
333 struct rk3308_grf *grf;
334 struct clk clk_speed;
335 int speed, ret;
336 enum {
337 RK3308_GMAC_SPEED_SHIFT = 0x0,
338 RK3308_GMAC_SPEED_MASK = BIT(0),
339 RK3308_GMAC_SPEED_10M = 0,
340 RK3308_GMAC_SPEED_100M = BIT(0),
341 };
342
343 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed",
344 &clk_speed);
345 if (ret)
346 return ret;
347
348 switch (priv->phydev->speed) {
349 case 10:
350 speed = RK3308_GMAC_SPEED_10M;
351 ret = clk_set_rate(&clk_speed, 2500000);
352 if (ret)
353 return ret;
354 break;
355 case 100:
356 speed = RK3308_GMAC_SPEED_100M;
357 ret = clk_set_rate(&clk_speed, 25000000);
358 if (ret)
359 return ret;
360 break;
361 default:
362 debug("Unknown phy speed: %d\n", priv->phydev->speed);
363 return -EINVAL;
364 }
365
366 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
367 rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed);
368
369 return 0;
370 }
371
rk3328_gmac_fix_mac_speed(struct gmac_rockchip_platdata * pdata,struct rockchip_eth_dev * dev)372 static int rk3328_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata,
373 struct rockchip_eth_dev *dev)
374 {
375 struct dw_eth_dev *priv = &dev->dw;
376 struct rk3328_grf_regs *grf;
377 int clk;
378 enum {
379 RK3328_GMAC_CLK_SEL_SHIFT = 11,
380 RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11),
381 RK3328_GMAC_CLK_SEL_125M = 0 << 11,
382 RK3328_GMAC_CLK_SEL_25M = 3 << 11,
383 RK3328_GMAC_CLK_SEL_2_5M = 2 << 11,
384
385 RK3328_GMAC_RMII_CLK_MASK = BIT(7),
386 RK3328_GMAC_RMII_CLK_2_5M = 0,
387 RK3328_GMAC_RMII_CLK_25M = BIT(7),
388
389 RK3328_GMAC_RMII_SPEED_MASK = BIT(2),
390 RK3328_GMAC_RMII_SPEED_10 = 0,
391 RK3328_GMAC_RMII_SPEED_100 = BIT(2),
392 };
393
394 switch (priv->phydev->speed) {
395 case 10:
396 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ?
397 (RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_RMII_SPEED_10) :
398 RK3328_GMAC_CLK_SEL_2_5M;
399 break;
400 case 100:
401 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ?
402 (RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_RMII_SPEED_100) :
403 RK3328_GMAC_CLK_SEL_25M;
404 break;
405 case 1000:
406 clk = RK3328_GMAC_CLK_SEL_125M;
407 break;
408 default:
409 debug("Unknown phy speed: %d\n", priv->phydev->speed);
410 return -EINVAL;
411 }
412
413 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
414 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1],
415 RK3328_GMAC_CLK_SEL_MASK |
416 RK3328_GMAC_RMII_CLK_MASK |
417 RK3328_GMAC_RMII_SPEED_MASK,
418 clk);
419
420 return 0;
421 }
422
rk3368_gmac_fix_mac_speed(struct gmac_rockchip_platdata * pdata,struct rockchip_eth_dev * dev)423 static int rk3368_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata,
424 struct rockchip_eth_dev *dev)
425 {
426 struct dw_eth_dev *priv = &dev->dw;
427 struct rk3368_grf *grf;
428 int clk;
429 enum {
430 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4,
431 RK3368_GMAC_CLK_SEL_25M = 3 << 4,
432 RK3368_GMAC_CLK_SEL_125M = 0 << 4,
433 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4),
434 };
435
436 switch (priv->phydev->speed) {
437 case 10:
438 clk = RK3368_GMAC_CLK_SEL_2_5M;
439 break;
440 case 100:
441 clk = RK3368_GMAC_CLK_SEL_25M;
442 break;
443 case 1000:
444 clk = RK3368_GMAC_CLK_SEL_125M;
445 break;
446 default:
447 debug("Unknown phy speed: %d\n", priv->phydev->speed);
448 return -EINVAL;
449 }
450
451 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
452 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk);
453
454 return 0;
455 }
456
rk3399_gmac_fix_mac_speed(struct gmac_rockchip_platdata * pdata,struct rockchip_eth_dev * dev)457 static int rk3399_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata,
458 struct rockchip_eth_dev *dev)
459 {
460 struct dw_eth_dev *priv = &dev->dw;
461 struct rk3399_grf_regs *grf;
462 int clk;
463
464 switch (priv->phydev->speed) {
465 case 10:
466 clk = RK3399_GMAC_CLK_SEL_2_5M;
467 break;
468 case 100:
469 clk = RK3399_GMAC_CLK_SEL_25M;
470 break;
471 case 1000:
472 clk = RK3399_GMAC_CLK_SEL_125M;
473 break;
474 default:
475 debug("Unknown phy speed: %d\n", priv->phydev->speed);
476 return -EINVAL;
477 }
478
479 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
480 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk);
481
482 return 0;
483 }
484
rv1108_set_rmii_speed(struct gmac_rockchip_platdata * pdata,struct rockchip_eth_dev * dev)485 static int rv1108_set_rmii_speed(struct gmac_rockchip_platdata *pdata,
486 struct rockchip_eth_dev *dev)
487 {
488 struct dw_eth_dev *priv = &dev->dw;
489 struct rv1108_grf *grf;
490 int clk, speed;
491 enum {
492 RV1108_GMAC_SPEED_MASK = BIT(2),
493 RV1108_GMAC_SPEED_10M = 0 << 2,
494 RV1108_GMAC_SPEED_100M = 1 << 2,
495 RV1108_GMAC_CLK_SEL_MASK = BIT(7),
496 RV1108_GMAC_CLK_SEL_2_5M = 0 << 7,
497 RV1108_GMAC_CLK_SEL_25M = 1 << 7,
498 };
499
500 switch (priv->phydev->speed) {
501 case 10:
502 clk = RV1108_GMAC_CLK_SEL_2_5M;
503 speed = RV1108_GMAC_SPEED_10M;
504 break;
505 case 100:
506 clk = RV1108_GMAC_CLK_SEL_25M;
507 speed = RV1108_GMAC_SPEED_100M;
508 break;
509 default:
510 debug("Unknown phy speed: %d\n", priv->phydev->speed);
511 return -EINVAL;
512 }
513
514 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
515 rk_clrsetreg(&grf->gmac_con0,
516 RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK,
517 clk | speed);
518
519 return 0;
520 }
521 #else
rk3528_set_rgmii_speed(struct gmac_rockchip_platdata * pdata,struct rockchip_eth_dev * dev)522 static int rk3528_set_rgmii_speed(struct gmac_rockchip_platdata *pdata,
523 struct rockchip_eth_dev *dev)
524 {
525 struct eqos_priv *priv = &dev->eqos;
526 struct rk3528_grf *grf;
527 unsigned int div;
528
529 enum {
530 RK3528_GMAC0_CLK_RMII_DIV_SHIFT = 3,
531 RK3528_GMAC0_CLK_RMII_DIV_MASK = GENMASK(4, 3),
532 RK3528_GMAC0_CLK_RMII_DIV2 = BIT(3),
533 RK3528_GMAC0_CLK_RMII_DIV20 = 0,
534 };
535
536 enum {
537 RK3528_GMAC1_CLK_RGMII_DIV_SHIFT = 10,
538 RK3528_GMAC1_CLK_RGMII_DIV_MASK = GENMASK(11, 10),
539 RK3528_GMAC1_CLK_RGMII_DIV1 = 0,
540 RK3528_GMAC1_CLK_RGMII_DIV5 = GENMASK(11, 10),
541 RK3528_GMAC1_CLK_RGMII_DIV50 = BIT(11),
542 RK3528_GMAC1_CLK_RMII_DIV2 = BIT(11),
543 RK3528_GMAC1_CLK_RMII_DIV20 = 0,
544 };
545
546 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
547
548 switch (priv->phy->speed) {
549 case 10:
550 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
551 div = pdata->bus_id ? RK3528_GMAC1_CLK_RMII_DIV20 :
552 RK3528_GMAC0_CLK_RMII_DIV20;
553 else
554 div = RK3528_GMAC1_CLK_RGMII_DIV50;
555 break;
556 case 100:
557 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
558 div = pdata->bus_id ? RK3528_GMAC1_CLK_RMII_DIV2 :
559 RK3528_GMAC0_CLK_RMII_DIV2;
560 else
561 div = RK3528_GMAC1_CLK_RGMII_DIV5;
562 break;
563 case 1000:
564 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII)
565 div = RK3528_GMAC1_CLK_RGMII_DIV1;
566 else
567 return -EINVAL;
568 break;
569 default:
570 debug("Unknown phy speed: %d\n", priv->phy->speed);
571 return -EINVAL;
572 }
573
574 if (pdata->bus_id)
575 rk_clrsetreg(&grf->gmac1_con0, RK3528_GMAC1_CLK_RGMII_DIV_MASK, div);
576 else
577 rk_clrsetreg(&grf->gmac0_con, RK3528_GMAC0_CLK_RMII_DIV_MASK, div);
578
579 return 0;
580 }
581
rk3562_set_gmac_speed(struct gmac_rockchip_platdata * pdata,struct rockchip_eth_dev * dev)582 static int rk3562_set_gmac_speed(struct gmac_rockchip_platdata *pdata,
583 struct rockchip_eth_dev *dev)
584 {
585 struct eqos_priv *priv = &dev->eqos;
586 struct rk3562_grf *grf;
587 unsigned int div;
588
589 enum {
590 RK3562_GMAC0_CLK_RGMII_DIV_SHIFT = 7,
591 RK3562_GMAC0_CLK_RGMII_DIV_MASK = GENMASK(8, 7),
592 RK3562_GMAC0_CLK_RGMII_DIV1 = 0,
593 RK3562_GMAC0_CLK_RGMII_DIV5 = GENMASK(8, 7),
594 RK3562_GMAC0_CLK_RGMII_DIV50 = BIT(8),
595 RK3562_GMAC0_CLK_RMII_DIV2 = BIT(7),
596 RK3562_GMAC0_CLK_RMII_DIV20 = 0,
597 };
598
599 enum {
600 RK3562_GMAC1_SPEED_SHIFT = 0x0,
601 RK3562_GMAC1_SPEED_MASK = BIT(0),
602 RK3562_GMAC1_SPEED_10M = 0,
603 RK3562_GMAC1_SPEED_100M = BIT(0),
604 };
605
606 enum {
607 RK3562_GMAC1_CLK_RMII_DIV_SHIFT = 13,
608 RK3562_GMAC1_CLK_RMII_DIV_MASK = BIT(13),
609 RK3562_GMAC1_CLK_RMII_DIV2 = BIT(13),
610 RK3562_GMAC1_CLK_RMII_DIV20 = 0,
611 };
612
613 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
614
615 switch (priv->phy->speed) {
616 case 10:
617 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) {
618 if (pdata->bus_id > 0) {
619 div = RK3562_GMAC1_CLK_RMII_DIV20;
620 rk_clrsetreg(&grf->soc_con[0],
621 RK3562_GMAC1_SPEED_MASK,
622 RK3562_GMAC1_SPEED_10M);
623 } else {
624 div = RK3562_GMAC0_CLK_RMII_DIV20;
625 }
626 } else {
627 div = RK3562_GMAC0_CLK_RGMII_DIV50;
628 }
629 break;
630 case 100:
631 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) {
632 if (pdata->bus_id > 0) {
633 div = RK3562_GMAC1_CLK_RMII_DIV2;
634 rk_clrsetreg(&grf->soc_con[0],
635 RK3562_GMAC1_SPEED_MASK,
636 RK3562_GMAC1_SPEED_100M);
637 } else {
638 div = RK3562_GMAC0_CLK_RMII_DIV2;
639 }
640 } else {
641 div = RK3562_GMAC0_CLK_RGMII_DIV5;
642 }
643 break;
644 case 1000:
645 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII)
646 div = RK3562_GMAC0_CLK_RGMII_DIV1;
647 else
648 return -EINVAL;
649 break;
650 default:
651 debug("Unknown phy speed: %d\n", priv->phy->speed);
652 return -EINVAL;
653 }
654
655 if (pdata->bus_id)
656 rk_clrsetreg(&grf->soc_con[1], RK3562_GMAC1_CLK_RMII_DIV_MASK, div);
657 else
658 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_CLK_RGMII_DIV_MASK, div);
659
660 return 0;
661 }
662
rk3588_set_rgmii_speed(struct gmac_rockchip_platdata * pdata,struct rockchip_eth_dev * dev)663 static int rk3588_set_rgmii_speed(struct gmac_rockchip_platdata *pdata,
664 struct rockchip_eth_dev *dev)
665 {
666 struct eqos_priv *priv = &dev->eqos;
667 struct rk3588_php_grf *php_grf;
668 unsigned int div, div_mask;
669
670 enum {
671 RK3588_GMAC_CLK_RGMII_DIV_SHIFT = 2,
672 RK3588_GMAC_CLK_RGMII_DIV_MASK = GENMASK(3, 2),
673 RK3588_GMAC_CLK_RGMII_DIV1 = 0,
674 RK3588_GMAC_CLK_RGMII_DIV5 = GENMASK(3, 2),
675 RK3588_GMAC_CLK_RGMII_DIV50 = BIT(3),
676 RK3588_GMAC_CLK_RMII_DIV2 = BIT(2),
677 RK3588_GMAC_CLK_RMII_DIV20 = 0,
678 RK3588_GMAC1_ID_SHIFT = 5,
679 };
680
681 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF);
682
683 switch (priv->phy->speed) {
684 case 10:
685 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
686 div = RK3588_GMAC_CLK_RMII_DIV20;
687 else
688 div = RK3588_GMAC_CLK_RGMII_DIV50;
689 break;
690 case 100:
691 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
692 div = RK3588_GMAC_CLK_RMII_DIV2;
693 else
694 div = RK3588_GMAC_CLK_RGMII_DIV5;
695 break;
696 case 1000:
697 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII)
698 div = RK3588_GMAC_CLK_RGMII_DIV1;
699 else
700 return -EINVAL;
701 break;
702 default:
703 debug("Unknown phy speed: %d\n", priv->phy->speed);
704 return -EINVAL;
705 }
706
707 if (pdata->bus_id == 1) {
708 div <<= 5;
709 div_mask = RK3588_GMAC_CLK_RGMII_DIV_MASK << 5;
710 }
711
712 div <<= pdata->bus_id ? RK3588_GMAC1_ID_SHIFT : 0;
713 div_mask = pdata->bus_id ? (RK3588_GMAC_CLK_RGMII_DIV_MASK << 5) :
714 RK3588_GMAC_CLK_RGMII_DIV_MASK;
715
716 rk_clrsetreg(&php_grf->clk_con1, div_mask, div);
717
718 return 0;
719 }
720
rv1106_set_rmii_speed(struct gmac_rockchip_platdata * pdata,struct rockchip_eth_dev * dev)721 static int rv1106_set_rmii_speed(struct gmac_rockchip_platdata *pdata,
722 struct rockchip_eth_dev *dev)
723 {
724 struct eqos_priv *priv = &dev->eqos;
725 struct rv1106_grf *grf;
726 unsigned int div;
727
728 enum {
729 RV1106_GMAC_CLK_RMII_DIV_SHIFT = 2,
730 RV1106_GMAC_CLK_RMII_DIV_MASK = GENMASK(3, 2),
731 RV1106_GMAC_CLK_RMII_DIV2 = BIT(2),
732 RV1106_GMAC_CLK_RMII_DIV20 = 0,
733 };
734
735 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
736
737 switch (priv->phy->speed) {
738 case 10:
739 div = RV1106_GMAC_CLK_RMII_DIV20;
740 break;
741 case 100:
742 div = RV1106_GMAC_CLK_RMII_DIV2;
743 break;
744 default:
745 debug("Unknown phy speed: %d\n", priv->phy->speed);
746 return -EINVAL;
747 }
748
749 rk_clrsetreg(&grf->gmac_clk_con, RV1106_GMAC_CLK_RMII_DIV_MASK, div);
750
751 return 0;
752 }
753
rv1126_set_rgmii_speed(struct gmac_rockchip_platdata * pdata,struct rockchip_eth_dev * dev)754 static int rv1126_set_rgmii_speed(struct gmac_rockchip_platdata *pdata,
755 struct rockchip_eth_dev *dev)
756 {
757 struct eqos_priv *priv = &dev->eqos;
758 struct clk clk_speed;
759 int ret;
760
761 ret = clk_get_by_name(priv->phy->dev, "clk_mac_speed",
762 &clk_speed);
763 if (ret) {
764 printf("%s can't get clk_mac_speed clock (ret=%d):\n",
765 __func__, ret);
766 return ret;
767 }
768
769 switch ( priv->phy->speed) {
770 case 10:
771 ret = clk_set_rate(&clk_speed, 2500000);
772 if (ret)
773 return ret;
774 break;
775 case 100:
776 ret = clk_set_rate(&clk_speed, 25000000);
777 if (ret)
778 return ret;
779 break;
780 case 1000:
781 ret = clk_set_rate(&clk_speed, 125000000);
782 if (ret)
783 return ret;
784 break;
785 default:
786 debug("Unknown phy speed: %d\n", priv->phy->speed);
787 return -EINVAL;
788 }
789
790 return 0;
791 }
792 #endif
793
794 #ifndef CONFIG_DWC_ETH_QOS
px30_gmac_set_to_rmii(struct gmac_rockchip_platdata * pdata)795 static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
796 {
797 struct px30_grf *grf;
798 enum {
799 px30_GMAC_PHY_INTF_SEL_SHIFT = 4,
800 px30_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 6),
801 px30_GMAC_PHY_INTF_SEL_RMII = BIT(6),
802 };
803
804 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
805
806 rk_clrsetreg(&grf->mac_con1,
807 px30_GMAC_PHY_INTF_SEL_MASK,
808 px30_GMAC_PHY_INTF_SEL_RMII);
809 }
810
rk1808_gmac_set_to_rgmii(struct gmac_rockchip_platdata * pdata)811 static void rk1808_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
812 {
813 struct rk1808_grf *grf;
814 enum {
815 RK1808_GMAC_PHY_INTF_SEL_SHIFT = 4,
816 RK1808_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
817 RK1808_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
818
819 RK1808_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
820 RK1808_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
821 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
822
823 RK1808_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
824 RK1808_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
825 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
826 };
827 enum {
828 RK1808_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8,
829 RK1808_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 7),
830
831 RK1808_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
832 RK1808_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0),
833 };
834
835 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
836 rk_clrsetreg(&grf->mac_con1,
837 RK1808_GMAC_PHY_INTF_SEL_MASK |
838 RK1808_RXCLK_DLY_ENA_GMAC_MASK |
839 RK1808_TXCLK_DLY_ENA_GMAC_MASK,
840 RK1808_GMAC_PHY_INTF_SEL_RGMII |
841 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE |
842 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE);
843
844 rk_clrsetreg(&grf->mac_con0,
845 RK1808_CLK_RX_DL_CFG_GMAC_MASK |
846 RK1808_CLK_TX_DL_CFG_GMAC_MASK,
847 (pdata->rx_delay << RK1808_CLK_RX_DL_CFG_GMAC_SHIFT) |
848 (pdata->tx_delay << RK1808_CLK_TX_DL_CFG_GMAC_SHIFT));
849 }
850
rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata * pdata)851 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
852 {
853 struct rk322x_grf *grf;
854 enum {
855 RK3228_RMII_MODE_SHIFT = 10,
856 RK3228_RMII_MODE_MASK = BIT(10),
857
858 RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4,
859 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
860 RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
861
862 RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
863 RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
864 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
865
866 RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
867 RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
868 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
869 };
870 enum {
871 RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
872 RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
873
874 RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
875 RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
876 };
877
878 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
879 rk_clrsetreg(&grf->mac_con[1],
880 RK3228_RMII_MODE_MASK |
881 RK3228_GMAC_PHY_INTF_SEL_MASK |
882 RK3228_RXCLK_DLY_ENA_GMAC_MASK |
883 RK3228_TXCLK_DLY_ENA_GMAC_MASK,
884 RK3228_GMAC_PHY_INTF_SEL_RGMII |
885 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE |
886 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE);
887
888 rk_clrsetreg(&grf->mac_con[0],
889 RK3228_CLK_RX_DL_CFG_GMAC_MASK |
890 RK3228_CLK_TX_DL_CFG_GMAC_MASK,
891 pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT |
892 pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT);
893 }
894
rk3228_gmac_set_to_rmii(struct gmac_rockchip_platdata * pdata)895 static void rk3228_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
896 {
897 struct rk322x_grf *grf;
898 enum {
899 RK3228_GRF_CON_RMII_MODE_MASK = BIT(11),
900 RK3228_GRF_CON_RMII_MODE_SEL = BIT(11),
901 RK3228_RMII_MODE_MASK = BIT(10),
902 RK3228_RMII_MODE_SEL = BIT(10),
903 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
904 RK3228_GMAC_PHY_INTF_SEL_RMII = BIT(6),
905 };
906
907 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
908 rk_clrsetreg(&grf->mac_con[1],
909 RK3228_GRF_CON_RMII_MODE_MASK |
910 RK3228_RMII_MODE_MASK |
911 RK3228_GMAC_PHY_INTF_SEL_MASK,
912 RK3228_GRF_CON_RMII_MODE_SEL |
913 RK3228_RMII_MODE_SEL |
914 RK3228_GMAC_PHY_INTF_SEL_RMII);
915 }
916
rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata * pdata)917 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
918 {
919 struct rk3288_grf *grf;
920
921 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
922 rk_clrsetreg(&grf->soc_con1,
923 RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK,
924 RK3288_GMAC_PHY_INTF_SEL_RGMII);
925
926 rk_clrsetreg(&grf->soc_con3,
927 RK3288_RXCLK_DLY_ENA_GMAC_MASK |
928 RK3288_TXCLK_DLY_ENA_GMAC_MASK |
929 RK3288_CLK_RX_DL_CFG_GMAC_MASK |
930 RK3288_CLK_TX_DL_CFG_GMAC_MASK,
931 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE |
932 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE |
933 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT |
934 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
935 }
936
rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata * pdata)937 static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
938 {
939 struct rk3308_grf *grf;
940 enum {
941 RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2,
942 RK3308_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 2),
943 RK3308_GMAC_PHY_INTF_SEL_RMII = BIT(4),
944 };
945
946 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
947
948 rk_clrsetreg(&grf->mac_con0,
949 RK3308_GMAC_PHY_INTF_SEL_MASK,
950 RK3308_GMAC_PHY_INTF_SEL_RMII);
951 }
952
rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata * pdata)953 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
954 {
955 struct rk3328_grf_regs *grf;
956 enum {
957 RK3328_RMII_MODE_SHIFT = 9,
958 RK3328_RMII_MODE_MASK = BIT(9),
959
960 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4,
961 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
962 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
963
964 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
965 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
966 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
967
968 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
969 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
970 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
971 };
972 enum {
973 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
974 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
975
976 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
977 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
978 };
979
980 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
981 rk_clrsetreg(&grf->mac_con[1],
982 RK3328_RMII_MODE_MASK |
983 RK3328_GMAC_PHY_INTF_SEL_MASK |
984 RK3328_RXCLK_DLY_ENA_GMAC_MASK |
985 RK3328_TXCLK_DLY_ENA_GMAC_MASK,
986 RK3328_GMAC_PHY_INTF_SEL_RGMII |
987 RK3328_RXCLK_DLY_ENA_GMAC_MASK |
988 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE);
989
990 rk_clrsetreg(&grf->mac_con[0],
991 RK3328_CLK_RX_DL_CFG_GMAC_MASK |
992 RK3328_CLK_TX_DL_CFG_GMAC_MASK,
993 pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT |
994 pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT);
995 }
996
rk3328_gmac_set_to_rmii(struct gmac_rockchip_platdata * pdata)997 static void rk3328_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
998 {
999 struct rk3328_grf_regs *grf;
1000 enum {
1001 RK3328_RMII_MODE_MASK = BIT(9),
1002 RK3328_RMII_MODE = BIT(9),
1003
1004 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
1005 RK3328_GMAC_PHY_INTF_SEL_RMII = BIT(6),
1006 };
1007
1008 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1009 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1],
1010 RK3328_RMII_MODE_MASK |
1011 RK3328_GMAC_PHY_INTF_SEL_MASK,
1012 RK3328_GMAC_PHY_INTF_SEL_RMII |
1013 RK3328_RMII_MODE);
1014 }
1015
rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata * pdata)1016 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
1017 {
1018 struct rk3368_grf *grf;
1019 enum {
1020 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9,
1021 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9),
1022 RK3368_RMII_MODE_MASK = BIT(6),
1023 RK3368_RMII_MODE = BIT(6),
1024 };
1025 enum {
1026 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15),
1027 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
1028 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15),
1029 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7),
1030 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
1031 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7),
1032 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
1033 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8),
1034 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
1035 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
1036 };
1037
1038 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1039 rk_clrsetreg(&grf->soc_con15,
1040 RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK,
1041 RK3368_GMAC_PHY_INTF_SEL_RGMII);
1042
1043 rk_clrsetreg(&grf->soc_con16,
1044 RK3368_RXCLK_DLY_ENA_GMAC_MASK |
1045 RK3368_TXCLK_DLY_ENA_GMAC_MASK |
1046 RK3368_CLK_RX_DL_CFG_GMAC_MASK |
1047 RK3368_CLK_TX_DL_CFG_GMAC_MASK,
1048 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE |
1049 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE |
1050 (pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT) |
1051 (pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT));
1052 }
1053
rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata * pdata)1054 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
1055 {
1056 struct rk3399_grf_regs *grf;
1057
1058 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1059
1060 rk_clrsetreg(&grf->soc_con5,
1061 RK3399_GMAC_PHY_INTF_SEL_MASK,
1062 RK3399_GMAC_PHY_INTF_SEL_RGMII);
1063
1064 rk_clrsetreg(&grf->soc_con6,
1065 RK3399_RXCLK_DLY_ENA_GMAC_MASK |
1066 RK3399_TXCLK_DLY_ENA_GMAC_MASK |
1067 RK3399_CLK_RX_DL_CFG_GMAC_MASK |
1068 RK3399_CLK_TX_DL_CFG_GMAC_MASK,
1069 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE |
1070 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE |
1071 (pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT) |
1072 (pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT));
1073 }
1074
rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata * pdata)1075 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
1076 {
1077 struct rv1108_grf *grf;
1078
1079 enum {
1080 RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
1081 RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4,
1082 };
1083
1084 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1085 rk_clrsetreg(&grf->gmac_con0,
1086 RV1108_GMAC_PHY_INTF_SEL_MASK,
1087 RV1108_GMAC_PHY_INTF_SEL_RMII);
1088 }
1089
rk3228_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata * pdata)1090 static void rk3228_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata)
1091 {
1092 struct rk322x_grf *grf;
1093 enum {
1094 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK = BIT(15),
1095 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY = BIT(15),
1096 };
1097 enum {
1098 RK3228_MACPHY_CFG_CLK_50M_MASK = BIT(14),
1099 RK3228_MACPHY_CFG_CLK_50M = BIT(14),
1100
1101 RK3228_MACPHY_RMII_MODE_MASK = GENMASK(7, 6),
1102 RK3228_MACPHY_RMII_MODE = BIT(6),
1103
1104 RK3228_MACPHY_ENABLE_MASK = BIT(0),
1105 RK3228_MACPHY_DISENABLE = 0,
1106 RK3228_MACPHY_ENABLE = BIT(0),
1107 };
1108 enum {
1109 RK3228_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0),
1110 RK3228_RK_GRF_CON2_MACPHY_ID = 0x1234,
1111 };
1112 enum {
1113 RK3228_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0),
1114 RK3228_RK_GRF_CON3_MACPHY_ID = 0x35,
1115 };
1116
1117 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1118 rk_clrsetreg(&grf->con_iomux,
1119 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK,
1120 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
1121
1122 rk_clrsetreg(&grf->macphy_con[2],
1123 RK3228_RK_GRF_CON2_MACPHY_ID_MASK,
1124 RK3228_RK_GRF_CON2_MACPHY_ID);
1125
1126 rk_clrsetreg(&grf->macphy_con[3],
1127 RK3228_RK_GRF_CON3_MACPHY_ID_MASK,
1128 RK3228_RK_GRF_CON3_MACPHY_ID);
1129
1130 /* disabled before trying to reset it &*/
1131 rk_clrsetreg(&grf->macphy_con[0],
1132 RK3228_MACPHY_CFG_CLK_50M_MASK |
1133 RK3228_MACPHY_RMII_MODE_MASK |
1134 RK3228_MACPHY_ENABLE_MASK,
1135 RK3228_MACPHY_CFG_CLK_50M |
1136 RK3228_MACPHY_RMII_MODE |
1137 RK3228_MACPHY_DISENABLE);
1138
1139 reset_assert(&pdata->phy_reset);
1140 udelay(10);
1141 reset_deassert(&pdata->phy_reset);
1142 udelay(10);
1143
1144 rk_clrsetreg(&grf->macphy_con[0],
1145 RK3228_MACPHY_ENABLE_MASK,
1146 RK3228_MACPHY_ENABLE);
1147 udelay(30 * 1000);
1148 }
1149
rk3328_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata * pdata)1150 static void rk3328_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata)
1151 {
1152 struct rk3328_grf_regs *grf;
1153 enum {
1154 RK3328_GRF_CON_RMII_MODE_MASK = BIT(9),
1155 RK3328_GRF_CON_RMII_MODE = BIT(9),
1156 };
1157 enum {
1158 RK3328_MACPHY_CFG_CLK_50M_MASK = BIT(14),
1159 RK3328_MACPHY_CFG_CLK_50M = BIT(14),
1160
1161 RK3328_MACPHY_RMII_MODE_MASK = GENMASK(7, 6),
1162 RK3328_MACPHY_RMII_MODE = BIT(6),
1163
1164 RK3328_MACPHY_ENABLE_MASK = BIT(0),
1165 RK3328_MACPHY_DISENABLE = 0,
1166 RK3328_MACPHY_ENABLE = BIT(0),
1167 };
1168 enum {
1169 RK3328_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0),
1170 RK3328_RK_GRF_CON2_MACPHY_ID = 0x1234,
1171 };
1172 enum {
1173 RK3328_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0),
1174 RK3328_RK_GRF_CON3_MACPHY_ID = 0x35,
1175 };
1176
1177 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1178 rk_clrsetreg(&grf->macphy_con[1],
1179 RK3328_GRF_CON_RMII_MODE_MASK,
1180 RK3328_GRF_CON_RMII_MODE);
1181
1182 rk_clrsetreg(&grf->macphy_con[2],
1183 RK3328_RK_GRF_CON2_MACPHY_ID_MASK,
1184 RK3328_RK_GRF_CON2_MACPHY_ID);
1185
1186 rk_clrsetreg(&grf->macphy_con[3],
1187 RK3328_RK_GRF_CON3_MACPHY_ID_MASK,
1188 RK3328_RK_GRF_CON3_MACPHY_ID);
1189
1190 /* disabled before trying to reset it &*/
1191 rk_clrsetreg(&grf->macphy_con[0],
1192 RK3328_MACPHY_CFG_CLK_50M_MASK |
1193 RK3328_MACPHY_RMII_MODE_MASK |
1194 RK3328_MACPHY_ENABLE_MASK,
1195 RK3328_MACPHY_CFG_CLK_50M |
1196 RK3328_MACPHY_RMII_MODE |
1197 RK3328_MACPHY_DISENABLE);
1198
1199 reset_assert(&pdata->phy_reset);
1200 udelay(10);
1201 reset_deassert(&pdata->phy_reset);
1202 udelay(10);
1203
1204 rk_clrsetreg(&grf->macphy_con[0],
1205 RK3328_MACPHY_ENABLE_MASK,
1206 RK3328_MACPHY_ENABLE);
1207 udelay(30 * 1000);
1208 }
1209
1210 #else
rk3528_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata * pdata)1211 static void rk3528_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata)
1212 {
1213 struct rk3528_grf *grf;
1214 unsigned char bgs[1] = {0};
1215
1216 enum {
1217 RK3528_MACPHY_ENABLE_MASK = BIT(1),
1218 RK3528_MACPHY_DISENABLE = BIT(1),
1219 RK3528_MACPHY_ENABLE = 0,
1220 RK3528_MACPHY_XMII_SEL_MASK = GENMASK(6, 5),
1221 RK3528_MACPHY_XMII_SEL = BIT(6),
1222 RK3528_MACPHY_24M_CLK_SEL_MASK = GENMASK(9, 7),
1223 RK3528_MACPHY_24M_CLK_SEL_24M = (BIT(8) | BIT(9)),
1224 RK3528_MACPHY_PHY_ID_MASK = GENMASK(14, 10),
1225 RK3528_MACPHY_PHY_ID = BIT(11),
1226 };
1227
1228 enum {
1229 RK3528_MACPHY_BGS_MASK = GENMASK(3, 0),
1230 };
1231
1232 #if defined(CONFIG_ROCKCHIP_EFUSE) || defined(CONFIG_ROCKCHIP_OTP)
1233 struct udevice *dev;
1234 u32 regs[2] = {0};
1235 ofnode node;
1236 int ret = 0;
1237
1238 /* retrieve the device */
1239 if (IS_ENABLED(CONFIG_ROCKCHIP_EFUSE))
1240 ret = uclass_get_device_by_driver(UCLASS_MISC,
1241 DM_GET_DRIVER(rockchip_efuse),
1242 &dev);
1243 else
1244 ret = uclass_get_device_by_driver(UCLASS_MISC,
1245 DM_GET_DRIVER(rockchip_otp),
1246 &dev);
1247 if (!ret) {
1248 node = dev_read_subnode(dev, "macphy-bgs");
1249 if (ofnode_valid(node)) {
1250 if (!ofnode_read_u32_array(node, "reg", regs, 2)) {
1251 /* read the bgs from the efuses */
1252 ret = misc_read(dev, regs[0], &bgs, 1);
1253 if (ret) {
1254 printf("read bgs from efuse/otp failed, ret=%d\n",
1255 ret);
1256 bgs[0] = 0;
1257 }
1258 }
1259 }
1260 }
1261 #endif
1262
1263 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1264
1265 reset_assert(&pdata->phy_reset);
1266 udelay(20);
1267 rk_clrsetreg(&grf->macphy_con0,
1268 RK3528_MACPHY_ENABLE_MASK |
1269 RK3528_MACPHY_XMII_SEL_MASK |
1270 RK3528_MACPHY_24M_CLK_SEL_MASK |
1271 RK3528_MACPHY_PHY_ID_MASK,
1272 RK3528_MACPHY_ENABLE |
1273 RK3528_MACPHY_XMII_SEL |
1274 RK3528_MACPHY_24M_CLK_SEL_24M |
1275 RK3528_MACPHY_PHY_ID);
1276
1277 rk_clrsetreg(&grf->macphy_con1,
1278 RK3528_MACPHY_BGS_MASK,
1279 bgs[0]);
1280 udelay(20);
1281 reset_deassert(&pdata->phy_reset);
1282 udelay(30 * 1000);
1283 }
1284
rk3528_set_to_rmii(struct gmac_rockchip_platdata * pdata)1285 static void rk3528_set_to_rmii(struct gmac_rockchip_platdata *pdata)
1286 {
1287 unsigned int clk_mode;
1288 struct rk3528_grf *grf;
1289
1290 enum {
1291 RK3528_GMAC0_CLK_RMII_MODE_SHIFT = 0x1,
1292 RK3528_GMAC0_CLK_RMII_MODE_MASK = BIT(1),
1293 RK3528_GMAC0_CLK_RMII_MODE = 0x1,
1294 };
1295
1296 enum {
1297 RK3528_GMAC1_CLK_RMII_MODE_SHIFT = 0x8,
1298 RK3528_GMAC1_CLK_RMII_MODE_MASK = BIT(8),
1299 RK3528_GMAC1_CLK_RMII_MODE = 0x1,
1300 };
1301
1302 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1303
1304 if (pdata->bus_id == 1) {
1305 clk_mode = RK3528_GMAC1_CLK_RMII_MODE << RK3528_GMAC1_CLK_RMII_MODE_SHIFT;
1306 rk_clrsetreg(&grf->gmac1_con1, RK3528_GMAC1_CLK_RMII_MODE_MASK, clk_mode);
1307 } else {
1308 clk_mode = RK3528_GMAC0_CLK_RMII_MODE << RK3528_GMAC0_CLK_RMII_MODE_SHIFT;
1309 rk_clrsetreg(&grf->gmac0_con, RK3528_GMAC0_CLK_RMII_MODE_MASK, clk_mode);
1310 }
1311 }
1312
rk3528_set_to_rgmii(struct gmac_rockchip_platdata * pdata)1313 static void rk3528_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
1314 {
1315 unsigned int rx_enable;
1316 unsigned int rx_delay;
1317 struct rk3528_grf *grf;
1318
1319 enum {
1320 RK3528_GMAC1_RGMII_MODE_SHIFT = 0x8,
1321 RK3528_GMAC1_RGMII_MODE_MASK = BIT(8),
1322 RK3528_GMAC1_RGMII_MODE = 0x0,
1323
1324 RK3528_GMAC1_TXCLK_DLY_ENA_MASK = BIT(14),
1325 RK3528_GMAC1_TXCLK_DLY_ENA_DISABLE = 0,
1326 RK3528_GMAC1_TXCLK_DLY_ENA_ENABLE = BIT(14),
1327
1328 RK3528_GMAC1_RXCLK_DLY_ENA_MASK = BIT(15),
1329 RK3528_GMAC1_RXCLK_DLY_ENA_DISABLE = 0,
1330 RK3528_GMAC1_RXCLK_DLY_ENA_ENABLE = BIT(15),
1331 };
1332
1333 enum {
1334 RK3528_GMAC1_RX_DL_CFG_SHIFT = 0x8,
1335 RK3528_GMAC1_RX_DL_CFG_MASK = GENMASK(15, 8),
1336
1337 RK3528_GMAC1_TX_DL_CFG_SHIFT = 0x0,
1338 RK3528_GMAC1_TX_DL_CFG_MASK = GENMASK(7, 0),
1339 };
1340
1341 if (!pdata->bus_id)
1342 return;
1343
1344 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1345
1346 if (pdata->rx_delay < 0) {
1347 rx_enable = RK3528_GMAC1_RXCLK_DLY_ENA_DISABLE;
1348 rx_delay = 0;
1349 } else {
1350 rx_enable = RK3528_GMAC1_RXCLK_DLY_ENA_ENABLE;
1351 rx_delay = pdata->rx_delay << RK3528_GMAC1_RX_DL_CFG_SHIFT;
1352 }
1353
1354 rk_clrsetreg(&grf->gmac1_con0,
1355 RK3528_GMAC1_TXCLK_DLY_ENA_MASK |
1356 RK3528_GMAC1_RXCLK_DLY_ENA_MASK |
1357 RK3528_GMAC1_RGMII_MODE_MASK,
1358 rx_enable | RK3528_GMAC1_TXCLK_DLY_ENA_ENABLE |
1359 (RK3528_GMAC1_RGMII_MODE << RK3528_GMAC1_RGMII_MODE_SHIFT));
1360
1361 rk_clrsetreg(&grf->gmac1_con1,
1362 RK3528_GMAC1_RX_DL_CFG_MASK |
1363 RK3528_GMAC1_TX_DL_CFG_MASK,
1364 (pdata->tx_delay << RK3528_GMAC1_TX_DL_CFG_SHIFT) |
1365 rx_delay);
1366 }
1367
rk3562_set_to_rmii(struct gmac_rockchip_platdata * pdata)1368 static void rk3562_set_to_rmii(struct gmac_rockchip_platdata *pdata)
1369 {
1370 struct rk3562_grf *grf;
1371 unsigned int mode;
1372
1373 enum {
1374 RK3562_GMAC0_RMII_MODE_SHIFT = 0x5,
1375 RK3562_GMAC0_RMII_MODE_MASK = BIT(5),
1376 RK3562_GMAC0_RMII_MODE = 0x1,
1377 };
1378
1379 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1380
1381 if (!pdata->bus_id) {
1382 mode = RK3562_GMAC0_RMII_MODE << RK3562_GMAC0_RMII_MODE_SHIFT;
1383 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_RMII_MODE_MASK, mode);
1384 }
1385 }
1386
rk3562_set_to_rgmii(struct gmac_rockchip_platdata * pdata)1387 static void rk3562_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
1388 {
1389 struct rk3562_grf *grf;
1390 struct rk3562_ioc *ioc;
1391 unsigned int rx_enable;
1392 unsigned int rx_delay;
1393
1394 enum {
1395 RK3562_GMAC0_RGMII_MODE_SHIFT = 0x5,
1396 RK3562_GMAC0_RGMII_MODE_MASK = BIT(5),
1397 RK3562_GMAC0_RGMII_MODE = 0x0,
1398
1399 RK3562_GMAC0_TXCLK_DLY_ENA_MASK = BIT(0),
1400 RK3562_GMAC0_TXCLK_DLY_ENA_DISABLE = 0,
1401 RK3562_GMAC0_TXCLK_DLY_ENA_ENABLE = BIT(0),
1402
1403 RK3562_GMAC0_RXCLK_DLY_ENA_MASK = BIT(1),
1404 RK3562_GMAC0_RXCLK_DLY_ENA_DISABLE = 0,
1405 RK3562_GMAC0_RXCLK_DLY_ENA_ENABLE = BIT(1),
1406 };
1407
1408 enum {
1409 RK3562_GMAC0_RX_DL_CFG_SHIFT = 0x8,
1410 RK3562_GMAC0_RX_DL_CFG_MASK = GENMASK(15, 8),
1411
1412 RK3562_GMAC0_TX_DL_CFG_SHIFT = 0x0,
1413 RK3562_GMAC0_TX_DL_CFG_MASK = GENMASK(7, 0),
1414 };
1415
1416 if (pdata->bus_id)
1417 return;
1418
1419 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1420 ioc = syscon_get_first_range(ROCKCHIP_SYSCON_IOC);
1421
1422 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_RGMII_MODE_MASK,
1423 RK3562_GMAC0_RGMII_MODE << RK3562_GMAC0_RGMII_MODE_SHIFT);
1424
1425 if (pdata->rx_delay < 0) {
1426 rx_enable = RK3562_GMAC0_RXCLK_DLY_ENA_DISABLE;
1427 rx_delay = 0;
1428 } else {
1429 rx_enable = RK3562_GMAC0_RXCLK_DLY_ENA_ENABLE;
1430 rx_delay = pdata->rx_delay << RK3562_GMAC0_RX_DL_CFG_SHIFT;
1431 }
1432
1433 rk_clrsetreg(&ioc->mac0_io_con1,
1434 RK3562_GMAC0_TXCLK_DLY_ENA_MASK |
1435 RK3562_GMAC0_RXCLK_DLY_ENA_MASK,
1436 rx_enable | RK3562_GMAC0_TXCLK_DLY_ENA_ENABLE);
1437
1438 rk_clrsetreg(&ioc->mac0_io_con0,
1439 RK3562_GMAC0_RX_DL_CFG_MASK |
1440 RK3562_GMAC0_TX_DL_CFG_MASK,
1441 (pdata->tx_delay << RK3562_GMAC0_TX_DL_CFG_SHIFT) |
1442 rx_delay);
1443
1444 rk_clrsetreg(&ioc->mac1_io_con1,
1445 RK3562_GMAC0_TXCLK_DLY_ENA_MASK |
1446 RK3562_GMAC0_RXCLK_DLY_ENA_MASK,
1447 rx_enable | RK3562_GMAC0_TXCLK_DLY_ENA_ENABLE);
1448
1449 rk_clrsetreg(&ioc->mac1_io_con0,
1450 RK3562_GMAC0_RX_DL_CFG_MASK |
1451 RK3562_GMAC0_TX_DL_CFG_MASK,
1452 (pdata->tx_delay << RK3562_GMAC0_TX_DL_CFG_SHIFT) |
1453 rx_delay);
1454 }
1455
rk3568_set_to_rmii(struct gmac_rockchip_platdata * pdata)1456 static void rk3568_set_to_rmii(struct gmac_rockchip_platdata *pdata)
1457 {
1458 struct rk3568_grf *grf;
1459 void *con1;
1460
1461 enum {
1462 RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4,
1463 RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
1464 RK3568_GMAC_PHY_INTF_SEL_RMII = BIT(6),
1465 };
1466
1467 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1468
1469 if (pdata->bus_id == 1)
1470 con1 = &grf->mac1_con1;
1471 else
1472 con1 = &grf->mac0_con1;
1473
1474 rk_clrsetreg(con1,
1475 RK3568_GMAC_PHY_INTF_SEL_MASK,
1476 RK3568_GMAC_PHY_INTF_SEL_RMII);
1477 }
1478
rk3568_set_to_rgmii(struct gmac_rockchip_platdata * pdata)1479 static void rk3568_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
1480 {
1481 struct rk3568_grf *grf;
1482 void *con0, *con1;
1483
1484 enum {
1485 RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4,
1486 RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
1487 RK3568_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
1488
1489 RK3568_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
1490 RK3568_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
1491 RK3568_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
1492
1493 RK3568_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
1494 RK3568_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
1495 RK3568_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
1496 };
1497
1498 enum {
1499 RK3568_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8,
1500 RK3568_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 8),
1501
1502 RK3568_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
1503 RK3568_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0),
1504 };
1505
1506 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1507
1508 if (pdata->bus_id == 1) {
1509 con0 = &grf->mac1_con0;
1510 con1 = &grf->mac1_con1;
1511 } else {
1512 con0 = &grf->mac0_con0;
1513 con1 = &grf->mac0_con1;
1514 }
1515
1516 rk_clrsetreg(con0,
1517 RK3568_CLK_RX_DL_CFG_GMAC_MASK |
1518 RK3568_CLK_TX_DL_CFG_GMAC_MASK,
1519 (pdata->rx_delay << RK3568_CLK_RX_DL_CFG_GMAC_SHIFT) |
1520 (pdata->tx_delay << RK3568_CLK_TX_DL_CFG_GMAC_SHIFT));
1521
1522 rk_clrsetreg(con1,
1523 RK3568_TXCLK_DLY_ENA_GMAC_MASK |
1524 RK3568_RXCLK_DLY_ENA_GMAC_MASK |
1525 RK3568_GMAC_PHY_INTF_SEL_MASK,
1526 RK3568_TXCLK_DLY_ENA_GMAC_ENABLE |
1527 RK3568_RXCLK_DLY_ENA_GMAC_ENABLE |
1528 RK3568_GMAC_PHY_INTF_SEL_RGMII);
1529 }
1530
rk3588_set_to_rmii(struct gmac_rockchip_platdata * pdata)1531 static void rk3588_set_to_rmii(struct gmac_rockchip_platdata *pdata)
1532 {
1533 unsigned int intf_sel, intf_sel_mask;
1534 unsigned int clk_mode, clk_mode_mask;
1535 struct rk3588_php_grf *php_grf;
1536
1537 enum {
1538 RK3588_GMAC_PHY_INTF_SEL_SHIFT = 3,
1539 RK3588_GMAC_PHY_INTF_SEL_MASK = GENMASK(5, 3),
1540 RK3588_GMAC_PHY_INTF_SEL_RMII = BIT(5),
1541 };
1542
1543 enum {
1544 RK3588_GMAC_CLK_RMII_MODE_SHIFT = 0x0,
1545 RK3588_GMAC_CLK_RMII_MODE_MASK = BIT(0),
1546 RK3588_GMAC_CLK_RMII_MODE = 0x1,
1547 };
1548
1549 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF);
1550
1551 if (pdata->bus_id == 1) {
1552 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RMII << 6;
1553 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK << 6;
1554 clk_mode = RK3588_GMAC_CLK_RMII_MODE << 5;
1555 clk_mode_mask = RK3588_GMAC_CLK_RMII_MODE_MASK << 5;
1556 } else {
1557 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RMII;
1558 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK;
1559 clk_mode = RK3588_GMAC_CLK_RMII_MODE;
1560 clk_mode_mask = RK3588_GMAC_CLK_RMII_MODE_MASK;
1561 }
1562
1563 rk_clrsetreg(&php_grf->gmac_con0, intf_sel_mask, intf_sel);
1564 rk_clrsetreg(&php_grf->clk_con1, clk_mode_mask, clk_mode);
1565 }
1566
rk3588_set_to_rgmii(struct gmac_rockchip_platdata * pdata)1567 static void rk3588_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
1568 {
1569 unsigned int rx_enable, rx_enable_mask, tx_enable, tx_enable_mask;
1570 unsigned int intf_sel, intf_sel_mask;
1571 unsigned int clk_mode, clk_mode_mask;
1572 unsigned int rx_delay;
1573 struct rk3588_php_grf *php_grf;
1574 struct rk3588_sys_grf *grf;
1575 void *offset_con;
1576
1577 enum {
1578 RK3588_GMAC_PHY_INTF_SEL_SHIFT = 3,
1579 RK3588_GMAC_PHY_INTF_SEL_MASK = GENMASK(5, 3),
1580 RK3588_GMAC_PHY_INTF_SEL_RGMII = BIT(3),
1581
1582 RK3588_RXCLK_DLY_ENA_GMAC_MASK = BIT(3),
1583 RK3588_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
1584 RK3588_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(3),
1585
1586 RK3588_TXCLK_DLY_ENA_GMAC_MASK = BIT(2),
1587 RK3588_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
1588 RK3588_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(2),
1589 };
1590
1591 enum {
1592 RK3588_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8,
1593 RK3588_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 8),
1594
1595 RK3588_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
1596 RK3588_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0),
1597 };
1598
1599 enum {
1600 RK3588_GMAC_CLK_RGMII_MODE_SHIFT = 0x0,
1601 RK3588_GMAC_CLK_RGMII_MODE_MASK = BIT(0),
1602 RK3588_GMAC_CLK_RGMII_MODE = 0x0,
1603 };
1604
1605 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1606 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF);
1607
1608 if (pdata->rx_delay < 0) {
1609 rx_enable = RK3588_RXCLK_DLY_ENA_GMAC_DISABLE;
1610 rx_delay = 0;
1611 } else {
1612 rx_enable = RK3588_RXCLK_DLY_ENA_GMAC_ENABLE;
1613 rx_delay = pdata->rx_delay << RK3588_CLK_RX_DL_CFG_GMAC_SHIFT;
1614 }
1615
1616 if (pdata->bus_id == 1) {
1617 offset_con = &grf->soc_con9;
1618 rx_enable = rx_delay << 2;
1619 rx_enable_mask = RK3588_RXCLK_DLY_ENA_GMAC_MASK << 2;
1620 tx_enable = RK3588_TXCLK_DLY_ENA_GMAC_ENABLE << 2;
1621 tx_enable_mask = RK3588_TXCLK_DLY_ENA_GMAC_MASK << 2;
1622 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RGMII << 6;
1623 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK << 6;
1624 clk_mode = RK3588_GMAC_CLK_RGMII_MODE << 5;
1625 clk_mode_mask = RK3588_GMAC_CLK_RGMII_MODE_MASK << 5;
1626 } else {
1627 offset_con = &grf->soc_con8;
1628 rx_enable_mask = RK3588_RXCLK_DLY_ENA_GMAC_MASK;
1629 tx_enable = RK3588_TXCLK_DLY_ENA_GMAC_ENABLE;
1630 tx_enable_mask = RK3588_TXCLK_DLY_ENA_GMAC_MASK;
1631 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RGMII;
1632 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK;
1633 clk_mode = RK3588_GMAC_CLK_RGMII_MODE;
1634 clk_mode_mask = RK3588_GMAC_CLK_RGMII_MODE_MASK;
1635 }
1636
1637 rk_clrsetreg(offset_con,
1638 RK3588_CLK_TX_DL_CFG_GMAC_MASK |
1639 RK3588_CLK_RX_DL_CFG_GMAC_MASK,
1640 (pdata->tx_delay << RK3588_CLK_TX_DL_CFG_GMAC_SHIFT) |
1641 rx_delay);
1642
1643 rk_clrsetreg(&grf->soc_con7, tx_enable_mask | rx_enable_mask,
1644 tx_enable | rx_enable);
1645
1646 rk_clrsetreg(&php_grf->gmac_con0, intf_sel_mask, intf_sel);
1647 rk_clrsetreg(&php_grf->clk_con1, clk_mode_mask, clk_mode);
1648 }
1649
rv1106_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata * pdata)1650 static void rv1106_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata)
1651 {
1652 struct rv1106_grf *grf;
1653 unsigned char bgs[1] = {0};
1654
1655 enum {
1656 RV1106_VOGRF_GMAC_CLK_RMII_MODE_MASK = BIT(0),
1657 RV1106_VOGRF_GMAC_CLK_RMII_MODE = BIT(0),
1658 };
1659
1660 enum {
1661 RV1106_MACPHY_ENABLE_MASK = BIT(1),
1662 RV1106_MACPHY_DISENABLE = BIT(1),
1663 RV1106_MACPHY_ENABLE = 0,
1664 RV1106_MACPHY_XMII_SEL_MASK = GENMASK(6, 5),
1665 RV1106_MACPHY_XMII_SEL = BIT(6),
1666 RV1106_MACPHY_24M_CLK_SEL_MASK = GENMASK(9, 7),
1667 RV1106_MACPHY_24M_CLK_SEL_24M = (BIT(8) | BIT(9)),
1668 RV1106_MACPHY_PHY_ID_MASK = GENMASK(14, 10),
1669 RV1106_MACPHY_PHY_ID = BIT(11),
1670 };
1671
1672 enum {
1673 RV1106_MACPHY_BGS_MASK = GENMASK(3, 0),
1674 RV1106_MACPHY_BGS = BIT(2),
1675 };
1676
1677 #if defined(CONFIG_ROCKCHIP_EFUSE) || defined(CONFIG_ROCKCHIP_OTP)
1678 struct udevice *dev;
1679 u32 regs[2] = {0};
1680 ofnode node;
1681 int ret = 0;
1682
1683 /* retrieve the device */
1684 if (IS_ENABLED(CONFIG_ROCKCHIP_EFUSE))
1685 ret = uclass_get_device_by_driver(UCLASS_MISC,
1686 DM_GET_DRIVER(rockchip_efuse),
1687 &dev);
1688 else
1689 ret = uclass_get_device_by_driver(UCLASS_MISC,
1690 DM_GET_DRIVER(rockchip_otp),
1691 &dev);
1692 if (!ret) {
1693 node = dev_read_subnode(dev, "macphy-bgs");
1694 if (ofnode_valid(node)) {
1695 if (!ofnode_read_u32_array(node, "reg", regs, 2)) {
1696 /* read the bgs from the efuses */
1697 ret = misc_read(dev, regs[0], &bgs, 1);
1698 if (ret) {
1699 printf("read bgs from efuse/otp failed, ret=%d\n",
1700 ret);
1701 bgs[0] = 0;
1702 }
1703 }
1704 }
1705 }
1706 #endif
1707
1708 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1709
1710 reset_assert(&pdata->phy_reset);
1711 udelay(20);
1712 rk_clrsetreg(&grf->macphy_con0,
1713 RV1106_MACPHY_ENABLE_MASK |
1714 RV1106_MACPHY_XMII_SEL_MASK |
1715 RV1106_MACPHY_24M_CLK_SEL_MASK |
1716 RV1106_MACPHY_PHY_ID_MASK,
1717 RV1106_MACPHY_ENABLE |
1718 RV1106_MACPHY_XMII_SEL |
1719 RV1106_MACPHY_24M_CLK_SEL_24M |
1720 RV1106_MACPHY_PHY_ID);
1721
1722 rk_clrsetreg(&grf->macphy_con1,
1723 RV1106_MACPHY_BGS_MASK,
1724 bgs[0]);
1725 udelay(20);
1726 reset_deassert(&pdata->phy_reset);
1727 udelay(30 * 1000);
1728 }
1729
rv1106_set_to_rmii(struct gmac_rockchip_platdata * pdata)1730 static void rv1106_set_to_rmii(struct gmac_rockchip_platdata *pdata)
1731 {
1732 struct rv1106_grf *grf;
1733 enum {
1734 RV1106_VOGRF_GMAC_CLK_RMII_MODE_MASK = BIT(0),
1735 RV1106_VOGRF_GMAC_CLK_RMII_MODE = BIT(0),
1736 };
1737
1738 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1739 rk_clrsetreg(&grf->gmac_clk_con,
1740 RV1106_VOGRF_GMAC_CLK_RMII_MODE_MASK,
1741 RV1106_VOGRF_GMAC_CLK_RMII_MODE);
1742 };
1743
rv1126_set_to_rmii(struct gmac_rockchip_platdata * pdata)1744 static void rv1126_set_to_rmii(struct gmac_rockchip_platdata *pdata)
1745 {
1746 struct rv1126_grf *grf;
1747
1748 enum {
1749 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4,
1750 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
1751 RV1126_GMAC_PHY_INTF_SEL_RMII = BIT(6),
1752 };
1753
1754 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1755
1756 rk_clrsetreg(&grf->mac_con0,
1757 RV1126_GMAC_PHY_INTF_SEL_MASK,
1758 RV1126_GMAC_PHY_INTF_SEL_RMII);
1759 }
1760
rv1126_set_to_rgmii(struct gmac_rockchip_platdata * pdata)1761 static void rv1126_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
1762 {
1763 struct rv1126_grf *grf;
1764
1765 enum {
1766 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4,
1767 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
1768 RV1126_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
1769
1770 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK = BIT(3),
1771 RV1126_RXCLK_M1_DLY_ENA_GMAC_DISABLE = 0,
1772 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(3),
1773
1774 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK = BIT(2),
1775 RV1126_TXCLK_M1_DLY_ENA_GMAC_DISABLE = 0,
1776 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(2),
1777
1778 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK = BIT(1),
1779 RV1126_RXCLK_M0_DLY_ENA_GMAC_DISABLE = 0,
1780 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(1),
1781
1782 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK = BIT(0),
1783 RV1126_TXCLK_M0_DLY_ENA_GMAC_DISABLE = 0,
1784 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(0),
1785 };
1786 enum {
1787 RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8,
1788 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8),
1789
1790 RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
1791 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
1792 };
1793 enum {
1794 RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8,
1795 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8),
1796
1797 RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
1798 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
1799 };
1800
1801 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1802
1803 rk_clrsetreg(&grf->mac_con0,
1804 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK |
1805 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK |
1806 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK |
1807 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK |
1808 RV1126_GMAC_PHY_INTF_SEL_MASK,
1809 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE |
1810 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE |
1811 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE |
1812 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE |
1813 RV1126_GMAC_PHY_INTF_SEL_RGMII);
1814
1815 rk_clrsetreg(&grf->mac_con1,
1816 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK |
1817 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK,
1818 (pdata->rx_delay << RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT) |
1819 (pdata->tx_delay << RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT));
1820
1821 rk_clrsetreg(&grf->mac_con2,
1822 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK |
1823 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK,
1824 (pdata->rx_delay << RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT) |
1825 (pdata->tx_delay << RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT));
1826 }
1827 #endif
1828
1829 #ifdef CONFIG_DWC_ETH_QOS
rk3528_set_clock_selection(struct gmac_rockchip_platdata * pdata)1830 static void rk3528_set_clock_selection(struct gmac_rockchip_platdata *pdata)
1831 {
1832 struct rk3528_grf *grf;
1833 unsigned int val;
1834
1835 enum {
1836 RK3528_GMAC1_CLK_SELET_SHIFT = 0x12,
1837 RK3528_GMAC1_CLK_SELET_MASK = BIT(12),
1838 RK3528_GMAC1_CLK_SELET_CRU = 0,
1839 RK3528_GMAC1_CLK_SELET_IO = BIT(12),
1840 };
1841
1842 if (!pdata->bus_id)
1843 return;
1844 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1845
1846 val = pdata->clock_input ? RK3528_GMAC1_CLK_SELET_IO :
1847 RK3528_GMAC1_CLK_SELET_CRU;
1848 rk_clrsetreg(&grf->gmac1_con0, RK3528_GMAC1_CLK_SELET_MASK, val);
1849 }
1850
rk3562_set_clock_selection(struct gmac_rockchip_platdata * pdata)1851 static void rk3562_set_clock_selection(struct gmac_rockchip_platdata *pdata)
1852 {
1853 struct rk3562_grf *grf;
1854 struct rk3562_ioc *ioc;
1855 unsigned int val;
1856
1857 enum {
1858 RK3562_GMAC0_CLK_SELET_SHIFT = 0x9,
1859 RK3562_GMAC0_CLK_SELET_MASK = BIT(9),
1860 RK3562_GMAC0_CLK_SELET_CRU = 0,
1861 RK3562_GMAC0_CLK_SELET_IO = BIT(9),
1862 };
1863
1864 enum {
1865 RK3562_GMAC1_CLK_SELET_SHIFT = 15,
1866 RK3562_GMAC1_CLK_SELET_MASK = BIT(15),
1867 RK3562_GMAC1_CLK_SELET_CRU = 0,
1868 RK3562_GMAC1_CLK_SELET_IO = BIT(15),
1869 };
1870
1871 enum {
1872 RK3562_GMAC0_IO_EXTCLK_SELET_SHIFT = 0x2,
1873 RK3562_GMAC0_IO_EXTCLK_SELET_MASK = BIT(2),
1874 RK3562_GMAC0_IO_EXTCLK_SELET_CRU = 0,
1875 RK3562_GMAC0_IO_EXTCLK_SELET_IO = BIT(2),
1876 };
1877
1878 enum {
1879 RK3562_GMAC1_IO_EXTCLK_SELET_SHIFT = 0x3,
1880 RK3562_GMAC1_IO_EXTCLK_SELET_MASK = BIT(3),
1881 RK3562_GMAC1_IO_EXTCLK_SELET_CRU = 0,
1882 RK3562_GMAC1_IO_EXTCLK_SELET_IO = BIT(3),
1883 };
1884
1885 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1886 ioc = syscon_get_first_range(ROCKCHIP_SYSCON_IOC);
1887
1888 if (!pdata->bus_id) {
1889 val = pdata->clock_input ? RK3562_GMAC0_CLK_SELET_IO :
1890 RK3562_GMAC0_CLK_SELET_CRU;
1891 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_CLK_SELET_MASK, val);
1892 val = pdata->clock_input ? RK3562_GMAC0_IO_EXTCLK_SELET_IO :
1893 RK3562_GMAC0_IO_EXTCLK_SELET_CRU;
1894 rk_clrsetreg(&ioc->mac1_io_con1,
1895 RK3562_GMAC0_IO_EXTCLK_SELET_MASK, val);
1896 rk_clrsetreg(&ioc->mac0_io_con1,
1897 RK3562_GMAC0_IO_EXTCLK_SELET_MASK, val);
1898
1899 } else {
1900 val = pdata->clock_input ? RK3562_GMAC1_CLK_SELET_IO :
1901 RK3562_GMAC1_CLK_SELET_CRU;
1902 rk_clrsetreg(&grf->soc_con[1], RK3562_GMAC1_CLK_SELET_MASK, val);
1903 val = pdata->clock_input ? RK3562_GMAC1_IO_EXTCLK_SELET_IO :
1904 RK3562_GMAC1_IO_EXTCLK_SELET_CRU;
1905 rk_clrsetreg(&ioc->mac1_io_con1,
1906 RK3562_GMAC1_IO_EXTCLK_SELET_MASK, val);
1907 }
1908 }
1909
rk3588_set_clock_selection(struct gmac_rockchip_platdata * pdata)1910 static void rk3588_set_clock_selection(struct gmac_rockchip_platdata *pdata)
1911 {
1912 struct rk3588_php_grf *php_grf;
1913 unsigned int val, mask;
1914
1915 enum {
1916 RK3588_GMAC_CLK_SELET_SHIFT = 0x4,
1917 RK3588_GMAC_CLK_SELET_MASK = BIT(4),
1918 RK3588_GMAC_CLK_SELET_CRU = BIT(4),
1919 RK3588_GMAC_CLK_SELET_IO = 0,
1920 };
1921
1922 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF);
1923 val = pdata->clock_input ? RK3588_GMAC_CLK_SELET_IO :
1924 RK3588_GMAC_CLK_SELET_CRU;
1925 mask = RK3588_GMAC_CLK_SELET_MASK;
1926
1927 if (pdata->bus_id == 1) {
1928 val <<= 5;
1929 mask <<= 5;
1930 }
1931
1932 rk_clrsetreg(&php_grf->clk_con1, mask, val);
1933 }
1934 #endif
1935
gmac_rockchip_probe(struct udevice * dev)1936 static int gmac_rockchip_probe(struct udevice *dev)
1937 {
1938 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
1939 struct rk_gmac_ops *ops =
1940 (struct rk_gmac_ops *)dev_get_driver_data(dev);
1941 #ifdef CONFIG_DWC_ETH_QOS
1942 struct eqos_config *config;
1943 #else
1944 struct dw_eth_pdata *dw_pdata;
1945 #endif
1946 struct eth_pdata *eth_pdata;
1947 struct clk clk;
1948 ulong rate;
1949 int ret;
1950
1951 #ifdef CONFIG_DWC_ETH_QOS
1952 eth_pdata = &pdata->eth_pdata;
1953 config = (struct eqos_config *)&ops->config;
1954 memcpy(config, &eqos_rockchip_config, sizeof(struct eqos_config));
1955 eth_pdata->phy_interface = config->ops->eqos_get_interface(dev);
1956 #else
1957 dw_pdata = &pdata->dw_eth_pdata;
1958 eth_pdata = &dw_pdata->eth_pdata;
1959 #endif
1960 pdata->bus_id = dev->seq;
1961
1962 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
1963 ret = clk_set_defaults(dev);
1964 if (ret)
1965 debug("%s clk_set_defaults failed %d\n", __func__, ret);
1966
1967 ret = clk_get_by_index(dev, 0, &clk);
1968 if (ret)
1969 return ret;
1970
1971 pdata->phy_interface = eth_pdata->phy_interface;
1972
1973 if (ops->set_clock_selection)
1974 ops->set_clock_selection(pdata);
1975
1976 if (pdata->integrated_phy && ops->integrated_phy_powerup)
1977 ops->integrated_phy_powerup(pdata);
1978
1979 switch (eth_pdata->phy_interface) {
1980 case PHY_INTERFACE_MODE_RGMII:
1981 case PHY_INTERFACE_MODE_RGMII_RXID:
1982 /*
1983 * If the gmac clock is from internal pll, need to set and
1984 * check the return value for gmac clock at RGMII mode. If
1985 * the gmac clock is from external source, the clock rate
1986 * is not set, because of it is bypassed.
1987 */
1988 if (!pdata->clock_input) {
1989 rate = clk_set_rate(&clk, 125000000);
1990 if (rate != 125000000)
1991 return -EINVAL;
1992 }
1993
1994 if (eth_pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
1995 pdata->rx_delay = -1;
1996
1997 /* Set to RGMII mode */
1998 if (ops->set_to_rgmii)
1999 ops->set_to_rgmii(pdata);
2000 else
2001 return -EPERM;
2002
2003 break;
2004 case PHY_INTERFACE_MODE_RMII:
2005 /* The commet is the same as RGMII mode */
2006 if (!pdata->clock_input) {
2007 rate = clk_set_rate(&clk, 50000000);
2008 if (rate != 50000000)
2009 return -EINVAL;
2010 }
2011
2012 /* Set to RMII mode */
2013 if (ops->set_to_rmii)
2014 ops->set_to_rmii(pdata);
2015
2016 break;
2017 default:
2018 debug("NO interface defined!\n");
2019 return -ENXIO;
2020 }
2021
2022 #ifdef CONFIG_DWC_ETH_QOS
2023 return eqos_probe(dev);
2024 #else
2025 return designware_eth_probe(dev);
2026 #endif
2027 }
2028
gmac_rockchip_eth_write_hwaddr(struct udevice * dev)2029 static int gmac_rockchip_eth_write_hwaddr(struct udevice *dev)
2030 {
2031 #if defined(CONFIG_DWC_ETH_QOS)
2032 return eqos_write_hwaddr(dev);
2033 #else
2034 return designware_eth_write_hwaddr(dev);
2035 #endif
2036 }
2037
gmac_rockchip_eth_free_pkt(struct udevice * dev,uchar * packet,int length)2038 static int gmac_rockchip_eth_free_pkt(struct udevice *dev, uchar *packet,
2039 int length)
2040 {
2041 #ifdef CONFIG_DWC_ETH_QOS
2042 return eqos_free_pkt(dev, packet, length);
2043 #else
2044 return designware_eth_free_pkt(dev, packet, length);
2045 #endif
2046 }
2047
gmac_rockchip_eth_send(struct udevice * dev,void * packet,int length)2048 static int gmac_rockchip_eth_send(struct udevice *dev, void *packet,
2049 int length)
2050 {
2051 #ifdef CONFIG_DWC_ETH_QOS
2052 return eqos_send(dev, packet, length);
2053 #else
2054 return designware_eth_send(dev, packet, length);
2055 #endif
2056 }
2057
gmac_rockchip_eth_recv(struct udevice * dev,int flags,uchar ** packetp)2058 static int gmac_rockchip_eth_recv(struct udevice *dev, int flags,
2059 uchar **packetp)
2060 {
2061 #ifdef CONFIG_DWC_ETH_QOS
2062 return eqos_recv(dev, flags, packetp);
2063 #else
2064 return designware_eth_recv(dev, flags, packetp);
2065 #endif
2066 }
2067
gmac_rockchip_eth_start(struct udevice * dev)2068 static int gmac_rockchip_eth_start(struct udevice *dev)
2069 {
2070 struct rockchip_eth_dev *priv = dev_get_priv(dev);
2071 struct rk_gmac_ops *ops =
2072 (struct rk_gmac_ops *)dev_get_driver_data(dev);
2073 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
2074 #ifndef CONFIG_DWC_ETH_QOS
2075 struct dw_eth_pdata *dw_pdata;
2076 struct eth_pdata *eth_pdata;
2077 #endif
2078 int ret;
2079
2080 #ifdef CONFIG_DWC_ETH_QOS
2081 ret = eqos_init(dev);
2082 #else
2083 dw_pdata = &pdata->dw_eth_pdata;
2084 eth_pdata = &dw_pdata->eth_pdata;
2085 ret = designware_eth_init((struct dw_eth_dev *)priv,
2086 eth_pdata->enetaddr);
2087 #endif
2088 if (ret)
2089 return ret;
2090 ret = ops->fix_mac_speed(pdata, priv);
2091 if (ret)
2092 return ret;
2093
2094 #ifdef CONFIG_DWC_ETH_QOS
2095 eqos_enable(dev);
2096 #else
2097 ret = designware_eth_enable((struct dw_eth_dev *)priv);
2098 if (ret)
2099 return ret;
2100 #endif
2101
2102 return 0;
2103 }
2104
gmac_rockchip_eth_stop(struct udevice * dev)2105 static void gmac_rockchip_eth_stop(struct udevice *dev)
2106 {
2107 #ifdef CONFIG_DWC_ETH_QOS
2108 eqos_stop(dev);
2109 #else
2110 designware_eth_stop(dev);
2111 #endif
2112 }
2113
2114 const struct eth_ops gmac_rockchip_eth_ops = {
2115 .start = gmac_rockchip_eth_start,
2116 .send = gmac_rockchip_eth_send,
2117 .recv = gmac_rockchip_eth_recv,
2118 .free_pkt = gmac_rockchip_eth_free_pkt,
2119 .stop = gmac_rockchip_eth_stop,
2120 .write_hwaddr = gmac_rockchip_eth_write_hwaddr,
2121 };
2122
2123 #ifndef CONFIG_DWC_ETH_QOS
2124 const struct rk_gmac_ops px30_gmac_ops = {
2125 .fix_mac_speed = px30_gmac_fix_mac_speed,
2126 .set_to_rmii = px30_gmac_set_to_rmii,
2127 };
2128
2129 const struct rk_gmac_ops rk1808_gmac_ops = {
2130 .fix_mac_speed = rk1808_gmac_fix_mac_speed,
2131 .set_to_rgmii = rk1808_gmac_set_to_rgmii,
2132 };
2133
2134 const struct rk_gmac_ops rk3228_gmac_ops = {
2135 .fix_mac_speed = rk3228_gmac_fix_mac_speed,
2136 .set_to_rmii = rk3228_gmac_set_to_rmii,
2137 .set_to_rgmii = rk3228_gmac_set_to_rgmii,
2138 .integrated_phy_powerup = rk3228_gmac_integrated_phy_powerup,
2139 };
2140
2141 const struct rk_gmac_ops rk3288_gmac_ops = {
2142 .fix_mac_speed = rk3288_gmac_fix_mac_speed,
2143 .set_to_rgmii = rk3288_gmac_set_to_rgmii,
2144 };
2145
2146 const struct rk_gmac_ops rk3308_gmac_ops = {
2147 .fix_mac_speed = rk3308_gmac_fix_mac_speed,
2148 .set_to_rmii = rk3308_gmac_set_to_rmii,
2149 };
2150
2151 const struct rk_gmac_ops rk3328_gmac_ops = {
2152 .fix_mac_speed = rk3328_gmac_fix_mac_speed,
2153 .set_to_rmii = rk3328_gmac_set_to_rmii,
2154 .set_to_rgmii = rk3328_gmac_set_to_rgmii,
2155 .integrated_phy_powerup = rk3328_gmac_integrated_phy_powerup,
2156 };
2157
2158 const struct rk_gmac_ops rk3368_gmac_ops = {
2159 .fix_mac_speed = rk3368_gmac_fix_mac_speed,
2160 .set_to_rgmii = rk3368_gmac_set_to_rgmii,
2161 };
2162
2163 const struct rk_gmac_ops rk3399_gmac_ops = {
2164 .fix_mac_speed = rk3399_gmac_fix_mac_speed,
2165 .set_to_rgmii = rk3399_gmac_set_to_rgmii,
2166 };
2167
2168 const struct rk_gmac_ops rv1108_gmac_ops = {
2169 .fix_mac_speed = rv1108_set_rmii_speed,
2170 .set_to_rmii = rv1108_gmac_set_to_rmii,
2171 };
2172 #else
2173 const struct rk_gmac_ops rk3528_gmac_ops = {
2174 .fix_mac_speed = rk3528_set_rgmii_speed,
2175 .set_to_rgmii = rk3528_set_to_rgmii,
2176 .set_to_rmii = rk3528_set_to_rmii,
2177 .set_clock_selection = rk3528_set_clock_selection,
2178 .integrated_phy_powerup = rk3528_gmac_integrated_phy_powerup,
2179 };
2180
2181 const struct rk_gmac_ops rk3562_gmac_ops = {
2182 .fix_mac_speed = rk3562_set_gmac_speed,
2183 .set_to_rgmii = rk3562_set_to_rgmii,
2184 .set_to_rmii = rk3562_set_to_rmii,
2185 .set_clock_selection = rk3562_set_clock_selection,
2186 };
2187
2188 const struct rk_gmac_ops rk3568_gmac_ops = {
2189 .fix_mac_speed = rv1126_set_rgmii_speed,
2190 .set_to_rgmii = rk3568_set_to_rgmii,
2191 .set_to_rmii = rk3568_set_to_rmii,
2192 };
2193
2194 const struct rk_gmac_ops rk3588_gmac_ops = {
2195 .fix_mac_speed = rk3588_set_rgmii_speed,
2196 .set_to_rgmii = rk3588_set_to_rgmii,
2197 .set_to_rmii = rk3588_set_to_rmii,
2198 .set_clock_selection = rk3588_set_clock_selection,
2199 };
2200
2201 const struct rk_gmac_ops rv1106_gmac_ops = {
2202 .fix_mac_speed = rv1106_set_rmii_speed,
2203 .set_to_rmii = rv1106_set_to_rmii,
2204 .integrated_phy_powerup = rv1106_gmac_integrated_phy_powerup,
2205 };
2206
2207 const struct rk_gmac_ops rv1126_gmac_ops = {
2208 .fix_mac_speed = rv1126_set_rgmii_speed,
2209 .set_to_rgmii = rv1126_set_to_rgmii,
2210 .set_to_rmii = rv1126_set_to_rmii,
2211 };
2212 #endif
2213
2214 static const struct udevice_id rockchip_gmac_ids[] = {
2215 #ifndef CONFIG_DWC_ETH_QOS
2216 #ifdef CONFIG_ROCKCHIP_PX30
2217 { .compatible = "rockchip,px30-gmac",
2218 .data = (ulong)&px30_gmac_ops },
2219 #endif
2220
2221 #ifdef CONFIG_ROCKCHIP_RK1808
2222 { .compatible = "rockchip,rk1808-gmac",
2223 .data = (ulong)&rk1808_gmac_ops },
2224 #endif
2225
2226 #ifdef CONFIG_ROCKCHIP_RK3228
2227 { .compatible = "rockchip,rk3228-gmac",
2228 .data = (ulong)&rk3228_gmac_ops },
2229 #endif
2230
2231 #ifdef CONFIG_ROCKCHIP_RK3288
2232 { .compatible = "rockchip,rk3288-gmac",
2233 .data = (ulong)&rk3288_gmac_ops },
2234 #endif
2235
2236 #ifdef CONFIG_ROCKCHIP_RK3308
2237 { .compatible = "rockchip,rk3308-mac",
2238 .data = (ulong)&rk3308_gmac_ops },
2239 #endif
2240
2241 #ifdef CONFIG_ROCKCHIP_RK3328
2242 { .compatible = "rockchip,rk3328-gmac",
2243 .data = (ulong)&rk3328_gmac_ops },
2244 #endif
2245
2246 #ifdef CONFIG_ROCKCHIP_RK3368
2247 { .compatible = "rockchip,rk3368-gmac",
2248 .data = (ulong)&rk3368_gmac_ops },
2249 #endif
2250
2251 #ifdef CONFIG_ROCKCHIP_RK3399
2252 { .compatible = "rockchip,rk3399-gmac",
2253 .data = (ulong)&rk3399_gmac_ops },
2254 #endif
2255
2256 #ifdef CONFIG_ROCKCHIP_RV1108
2257 { .compatible = "rockchip,rv1108-gmac",
2258 .data = (ulong)&rv1108_gmac_ops },
2259 #endif
2260 #else
2261 #ifdef CONFIG_ROCKCHIP_RK3528
2262 { .compatible = "rockchip,rk3528-gmac",
2263 .data = (ulong)&rk3528_gmac_ops },
2264 #endif
2265
2266 #ifdef CONFIG_ROCKCHIP_RK3562
2267 { .compatible = "rockchip,rk3562-gmac",
2268 .data = (ulong)&rk3562_gmac_ops },
2269 #endif
2270
2271 #ifdef CONFIG_ROCKCHIP_RK3568
2272 { .compatible = "rockchip,rk3568-gmac",
2273 .data = (ulong)&rk3568_gmac_ops },
2274 #endif
2275
2276 #ifdef CONFIG_ROCKCHIP_RK3588
2277 { .compatible = "rockchip,rk3588-gmac",
2278 .data = (ulong)&rk3588_gmac_ops },
2279 #endif
2280
2281 #ifdef CONFIG_ROCKCHIP_RV1106
2282 { .compatible = "rockchip,rv1106-gmac",
2283 .data = (ulong)&rv1106_gmac_ops },
2284 #endif
2285
2286 #ifdef CONFIG_ROCKCHIP_RV1126
2287 { .compatible = "rockchip,rv1126-gmac",
2288 .data = (ulong)&rv1126_gmac_ops },
2289 #endif
2290 #endif
2291 { }
2292 };
2293
2294 U_BOOT_DRIVER(eth_gmac_rockchip) = {
2295 .name = "gmac_rockchip",
2296 .id = UCLASS_ETH,
2297 .of_match = rockchip_gmac_ids,
2298 .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata,
2299 .probe = gmac_rockchip_probe,
2300 .ops = &gmac_rockchip_eth_ops,
2301 .priv_auto_alloc_size = sizeof(struct rockchip_eth_dev),
2302 .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata),
2303 .flags = DM_FLAG_ALLOC_PRIV_DMA,
2304 };
2305