1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Faraday FTMAC100 Ethernet 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2009 Faraday Technology 5*4882a593Smuzhiyun * Po-Yu Chuang <ratbert@faraday-tech.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __FTMAC100_H 11*4882a593Smuzhiyun #define __FTMAC100_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct ftmac100 { 14*4882a593Smuzhiyun unsigned int isr; /* 0x00 */ 15*4882a593Smuzhiyun unsigned int imr; /* 0x04 */ 16*4882a593Smuzhiyun unsigned int mac_madr; /* 0x08 */ 17*4882a593Smuzhiyun unsigned int mac_ladr; /* 0x0c */ 18*4882a593Smuzhiyun unsigned int maht0; /* 0x10 */ 19*4882a593Smuzhiyun unsigned int maht1; /* 0x14 */ 20*4882a593Smuzhiyun unsigned int txpd; /* 0x18 */ 21*4882a593Smuzhiyun unsigned int rxpd; /* 0x1c */ 22*4882a593Smuzhiyun unsigned int txr_badr; /* 0x20 */ 23*4882a593Smuzhiyun unsigned int rxr_badr; /* 0x24 */ 24*4882a593Smuzhiyun unsigned int itc; /* 0x28 */ 25*4882a593Smuzhiyun unsigned int aptc; /* 0x2c */ 26*4882a593Smuzhiyun unsigned int dblac; /* 0x30 */ 27*4882a593Smuzhiyun unsigned int pad1[3]; /* 0x34 - 0x3c */ 28*4882a593Smuzhiyun unsigned int pad2[16]; /* 0x40 - 0x7c */ 29*4882a593Smuzhiyun unsigned int pad3[2]; /* 0x80 - 0x84 */ 30*4882a593Smuzhiyun unsigned int maccr; /* 0x88 */ 31*4882a593Smuzhiyun unsigned int macsr; /* 0x8c */ 32*4882a593Smuzhiyun unsigned int phycr; /* 0x90 */ 33*4882a593Smuzhiyun unsigned int phywdata; /* 0x94 */ 34*4882a593Smuzhiyun unsigned int fcr; /* 0x98 */ 35*4882a593Smuzhiyun unsigned int bpr; /* 0x9c */ 36*4882a593Smuzhiyun unsigned int pad4[8]; /* 0xa0 - 0xbc */ 37*4882a593Smuzhiyun unsigned int pad5; /* 0xc0 */ 38*4882a593Smuzhiyun unsigned int ts; /* 0xc4 */ 39*4882a593Smuzhiyun unsigned int dmafifos; /* 0xc8 */ 40*4882a593Smuzhiyun unsigned int tm; /* 0xcc */ 41*4882a593Smuzhiyun unsigned int pad6; /* 0xd0 */ 42*4882a593Smuzhiyun unsigned int tx_mcol_scol; /* 0xd4 */ 43*4882a593Smuzhiyun unsigned int rpf_aep; /* 0xd8 */ 44*4882a593Smuzhiyun unsigned int xm_pg; /* 0xdc */ 45*4882a593Smuzhiyun unsigned int runt_tlcc; /* 0xe0 */ 46*4882a593Smuzhiyun unsigned int crcer_ftl; /* 0xe4 */ 47*4882a593Smuzhiyun unsigned int rlc_rcc; /* 0xe8 */ 48*4882a593Smuzhiyun unsigned int broc; /* 0xec */ 49*4882a593Smuzhiyun unsigned int mulca; /* 0xf0 */ 50*4882a593Smuzhiyun unsigned int rp; /* 0xf4 */ 51*4882a593Smuzhiyun unsigned int xp; /* 0xf8 */ 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* 55*4882a593Smuzhiyun * Interrupt status register & interrupt mask register 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun #define FTMAC100_INT_RPKT_FINISH (1 << 0) 58*4882a593Smuzhiyun #define FTMAC100_INT_NORXBUF (1 << 1) 59*4882a593Smuzhiyun #define FTMAC100_INT_XPKT_FINISH (1 << 2) 60*4882a593Smuzhiyun #define FTMAC100_INT_NOTXBUF (1 << 3) 61*4882a593Smuzhiyun #define FTMAC100_INT_XPKT_OK (1 << 4) 62*4882a593Smuzhiyun #define FTMAC100_INT_XPKT_LOST (1 << 5) 63*4882a593Smuzhiyun #define FTMAC100_INT_RPKT_SAV (1 << 6) 64*4882a593Smuzhiyun #define FTMAC100_INT_RPKT_LOST (1 << 7) 65*4882a593Smuzhiyun #define FTMAC100_INT_AHB_ERR (1 << 8) 66*4882a593Smuzhiyun #define FTMAC100_INT_PHYSTS_CHG (1 << 9) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* 69*4882a593Smuzhiyun * Automatic polling timer control register 70*4882a593Smuzhiyun */ 71*4882a593Smuzhiyun #define FTMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0) 72*4882a593Smuzhiyun #define FTMAC100_APTC_RXPOLL_TIME_SEL (1 << 4) 73*4882a593Smuzhiyun #define FTMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8) 74*4882a593Smuzhiyun #define FTMAC100_APTC_TXPOLL_TIME_SEL (1 << 12) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* 77*4882a593Smuzhiyun * MAC control register 78*4882a593Smuzhiyun */ 79*4882a593Smuzhiyun #define FTMAC100_MACCR_XDMA_EN (1 << 0) 80*4882a593Smuzhiyun #define FTMAC100_MACCR_RDMA_EN (1 << 1) 81*4882a593Smuzhiyun #define FTMAC100_MACCR_SW_RST (1 << 2) 82*4882a593Smuzhiyun #define FTMAC100_MACCR_LOOP_EN (1 << 3) 83*4882a593Smuzhiyun #define FTMAC100_MACCR_CRC_DIS (1 << 4) 84*4882a593Smuzhiyun #define FTMAC100_MACCR_XMT_EN (1 << 5) 85*4882a593Smuzhiyun #define FTMAC100_MACCR_ENRX_IN_HALFTX (1 << 6) 86*4882a593Smuzhiyun #define FTMAC100_MACCR_RCV_EN (1 << 8) 87*4882a593Smuzhiyun #define FTMAC100_MACCR_HT_MULTI_EN (1 << 9) 88*4882a593Smuzhiyun #define FTMAC100_MACCR_RX_RUNT (1 << 10) 89*4882a593Smuzhiyun #define FTMAC100_MACCR_RX_FTL (1 << 11) 90*4882a593Smuzhiyun #define FTMAC100_MACCR_RCV_ALL (1 << 12) 91*4882a593Smuzhiyun #define FTMAC100_MACCR_CRC_APD (1 << 14) 92*4882a593Smuzhiyun #define FTMAC100_MACCR_FULLDUP (1 << 15) 93*4882a593Smuzhiyun #define FTMAC100_MACCR_RX_MULTIPKT (1 << 16) 94*4882a593Smuzhiyun #define FTMAC100_MACCR_RX_BROADPKT (1 << 17) 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* 97*4882a593Smuzhiyun * Transmit descriptor, aligned to 16 bytes 98*4882a593Smuzhiyun */ 99*4882a593Smuzhiyun struct ftmac100_txdes { 100*4882a593Smuzhiyun unsigned int txdes0; 101*4882a593Smuzhiyun unsigned int txdes1; 102*4882a593Smuzhiyun unsigned int txdes2; /* TXBUF_BADR */ 103*4882a593Smuzhiyun unsigned int txdes3; /* not used by HW */ 104*4882a593Smuzhiyun } __attribute__ ((aligned(16))); 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #define FTMAC100_TXDES0_TXPKT_LATECOL (1 << 0) 107*4882a593Smuzhiyun #define FTMAC100_TXDES0_TXPKT_EXSCOL (1 << 1) 108*4882a593Smuzhiyun #define FTMAC100_TXDES0_TXDMA_OWN (1 << 31) 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #define FTMAC100_TXDES1_TXBUF_SIZE(x) ((x) & 0x7ff) 111*4882a593Smuzhiyun #define FTMAC100_TXDES1_LTS (1 << 27) 112*4882a593Smuzhiyun #define FTMAC100_TXDES1_FTS (1 << 28) 113*4882a593Smuzhiyun #define FTMAC100_TXDES1_TX2FIC (1 << 29) 114*4882a593Smuzhiyun #define FTMAC100_TXDES1_TXIC (1 << 30) 115*4882a593Smuzhiyun #define FTMAC100_TXDES1_EDOTR (1 << 31) 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* 118*4882a593Smuzhiyun * Receive descriptor, aligned to 16 bytes 119*4882a593Smuzhiyun */ 120*4882a593Smuzhiyun struct ftmac100_rxdes { 121*4882a593Smuzhiyun unsigned int rxdes0; 122*4882a593Smuzhiyun unsigned int rxdes1; 123*4882a593Smuzhiyun unsigned int rxdes2; /* RXBUF_BADR */ 124*4882a593Smuzhiyun unsigned int rxdes3; /* not used by HW */ 125*4882a593Smuzhiyun } __attribute__ ((aligned(16))); 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define FTMAC100_RXDES0_RFL(des) ((des) & 0x7ff) 128*4882a593Smuzhiyun #define FTMAC100_RXDES0_MULTICAST (1 << 16) 129*4882a593Smuzhiyun #define FTMAC100_RXDES0_BROADCAST (1 << 17) 130*4882a593Smuzhiyun #define FTMAC100_RXDES0_RX_ERR (1 << 18) 131*4882a593Smuzhiyun #define FTMAC100_RXDES0_CRC_ERR (1 << 19) 132*4882a593Smuzhiyun #define FTMAC100_RXDES0_FTL (1 << 20) 133*4882a593Smuzhiyun #define FTMAC100_RXDES0_RUNT (1 << 21) 134*4882a593Smuzhiyun #define FTMAC100_RXDES0_RX_ODD_NB (1 << 22) 135*4882a593Smuzhiyun #define FTMAC100_RXDES0_LRS (1 << 28) 136*4882a593Smuzhiyun #define FTMAC100_RXDES0_FRS (1 << 29) 137*4882a593Smuzhiyun #define FTMAC100_RXDES0_RXDMA_OWN (1 << 31) 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun #define FTMAC100_RXDES1_RXBUF_SIZE(x) ((x) & 0x7ff) 140*4882a593Smuzhiyun #define FTMAC100_RXDES1_EDORR (1 << 31) 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun #endif /* __FTMAC100_H */ 143