1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2009-2010, 2013 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun * Jun-jie Zhang <b18070@freescale.com>
4*4882a593Smuzhiyun * Mingkai Hu <Mingkai.hu@freescale.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <miiphy.h>
11*4882a593Smuzhiyun #include <phy.h>
12*4882a593Smuzhiyun #include <fsl_mdio.h>
13*4882a593Smuzhiyun #include <asm/io.h>
14*4882a593Smuzhiyun #include <linux/errno.h>
15*4882a593Smuzhiyun
tsec_local_mdio_write(struct tsec_mii_mng __iomem * phyregs,int port_addr,int dev_addr,int regnum,int value)16*4882a593Smuzhiyun void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
17*4882a593Smuzhiyun int dev_addr, int regnum, int value)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun int timeout = 1000000;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
22*4882a593Smuzhiyun out_be32(&phyregs->miimcon, value);
23*4882a593Smuzhiyun /* Memory barrier */
24*4882a593Smuzhiyun mb();
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun while ((in_be32(&phyregs->miimind) & MIIMIND_BUSY) && timeout--)
27*4882a593Smuzhiyun ;
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun
tsec_local_mdio_read(struct tsec_mii_mng __iomem * phyregs,int port_addr,int dev_addr,int regnum)30*4882a593Smuzhiyun int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr,
31*4882a593Smuzhiyun int dev_addr, int regnum)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun int value;
34*4882a593Smuzhiyun int timeout = 1000000;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* Put the address of the phy, and the register number into MIIMADD */
37*4882a593Smuzhiyun out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* Clear the command register, and wait */
40*4882a593Smuzhiyun out_be32(&phyregs->miimcom, 0);
41*4882a593Smuzhiyun /* Memory barrier */
42*4882a593Smuzhiyun mb();
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* Initiate a read command, and wait */
45*4882a593Smuzhiyun out_be32(&phyregs->miimcom, MIIMCOM_READ_CYCLE);
46*4882a593Smuzhiyun /* Memory barrier */
47*4882a593Smuzhiyun mb();
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* Wait for the the indication that the read is done */
50*4882a593Smuzhiyun while ((in_be32(&phyregs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
51*4882a593Smuzhiyun && timeout--)
52*4882a593Smuzhiyun ;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /* Grab the value read from the PHY */
55*4882a593Smuzhiyun value = in_be32(&phyregs->miimstat);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun return value;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
fsl_pq_mdio_reset(struct mii_dev * bus)60*4882a593Smuzhiyun static int fsl_pq_mdio_reset(struct mii_dev *bus)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun struct tsec_mii_mng __iomem *regs =
63*4882a593Smuzhiyun (struct tsec_mii_mng __iomem *)bus->priv;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* Reset MII (due to new addresses) */
66*4882a593Smuzhiyun out_be32(®s->miimcfg, MIIMCFG_RESET_MGMT);
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun out_be32(®s->miimcfg, MIIMCFG_INIT_VALUE);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun while (in_be32(®s->miimind) & MIIMIND_BUSY)
71*4882a593Smuzhiyun ;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun return 0;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
tsec_phy_read(struct mii_dev * bus,int addr,int dev_addr,int regnum)76*4882a593Smuzhiyun int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun struct tsec_mii_mng __iomem *phyregs =
79*4882a593Smuzhiyun (struct tsec_mii_mng __iomem *)bus->priv;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun return tsec_local_mdio_read(phyregs, addr, dev_addr, regnum);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
tsec_phy_write(struct mii_dev * bus,int addr,int dev_addr,int regnum,u16 value)84*4882a593Smuzhiyun int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
85*4882a593Smuzhiyun u16 value)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun struct tsec_mii_mng __iomem *phyregs =
88*4882a593Smuzhiyun (struct tsec_mii_mng __iomem *)bus->priv;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun tsec_local_mdio_write(phyregs, addr, dev_addr, regnum, value);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun return 0;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
fsl_pq_mdio_init(bd_t * bis,struct fsl_pq_mdio_info * info)95*4882a593Smuzhiyun int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun struct mii_dev *bus = mdio_alloc();
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun if (!bus) {
100*4882a593Smuzhiyun printf("Failed to allocate FSL MDIO bus\n");
101*4882a593Smuzhiyun return -1;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun bus->read = tsec_phy_read;
105*4882a593Smuzhiyun bus->write = tsec_phy_write;
106*4882a593Smuzhiyun bus->reset = fsl_pq_mdio_reset;
107*4882a593Smuzhiyun strcpy(bus->name, info->name);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun bus->priv = (void *)info->regs;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun return mdio_register(bus);
112*4882a593Smuzhiyun }
113